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24-bit, 192kHz AV Receiver on-a-Chip
DESCRIPTION
The WM8777 is a high performance, multi-channel audio codec. The WM8777 is ideal for surround sound processing applications for home hi-fi, automotive and other audio visual equipment. A S/PDIF transceiver with 4-channel input mux is included. Analogue domain bass management processing, and front channel analogue tone control facilities are provided. A stereo 24-bit multi-bit sigma delta ADC is used with a six stereo channel input selector. Each channel has analogue domain mute and programmable gain control. Sampling rates from 8kHz to 192kHz are supported. Four stereo 24-bit multi-bit sigma delta DACs are provided, which may be used to support up to 7.1 channel operation. If preferred, 5.1 operation may be chosen, with the spare stereo DAC used to support an Aux remote room. Sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. A set of input multiplexors allows switching of an external 5.1 analogue input, or bypass channel stereo analogue input into the signal path. The front channel analogue signals may be looped out of the chip prior to each master volume control, and external filtering applied in order to select treble and bass filter characteristics. Adjustment of tone controls is then achieved using on-chip gain adjust amplifiers, addressed via the control interface. Analogue bass management support is provided, plus analogue stereo mixdown options. The device is controlled via a serial interface giving access to all features including channel selection, volume controls, tone controls, mutes, de-emphasis and power management facilities. The device is available in a 100-pin LQFP package.
WM8777
FEATURES
* * * * * * AV receiver on-a-chip with 8 DACs and 2 ADCs Integrated S/PDIF/IEC60958/AES3 transceiver Analogue Bass Management and stereo mixdown support Analogue tone controls for front 3 channels Master volume control on each DAC channel with gain range of +20dB to -100dB in 1dB steps Audio Performance - 108dB SNR (`A' weighted @ 48kHz) DAC - 102dB SNR (`A' weighted @ 48kHz) ADC - 110dB SNR (`A' weighted) Analogue volume control DAC Sampling Frequency: 8KHz - 192kHz ADC Sampling Frequency: 8KHz - 192kHz 3-Wire SPI or 2-wire MPU Serial Control Interface with readback. Master or Slave Clocking Mode Programmable Format Audio Data Interface Modes Four Independent stereo DAC outputs with independent digital volume controls Integrated Stereo headphone amplifier with source select 5.1 channel analogue input prior to the tone controls, bass management and stereo mixdown functions. Six stereo input ADC mux with analogue gain adjust from +24dB to -21dB in 0.5dB steps 5V Analogue, 2.7V to 3.6V Digital supply Operation
* * * * * * * * * *
APPLICATIONS
* Surround Sound AV Processors and Hi-Fi systems
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
Product Preview, November 2004, Rev 1.94
Copyright 2004 Wolfson Microelectronics plc
WM8777 TABLE OF CONTENTS
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DESCRIPTION .......................................................................................................1 FEATURES.............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION...........................................................................................3 ORDERING INFORMATION ..................................................................................3 PIN DESCRIPTION ................................................................................................4 ABSOLUTE MAXIMUM RATINGS.........................................................................6 RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY .......................................................................................................... 10
SUPPLY CURRENT .............................................................................................11 DEVICE DESCRIPTION .......................................................................................12
INTRODUCTION ......................................................................................................... 12 ANALOGUE TONE CONTROLS ................................................................................. 13 BASS MANAGEMENT................................................................................................. 19 HEADPHONE OUTPUT .............................................................................................. 20 OUTPUT POWERDOWN............................................................................................ 21 DIGITAL AUDIO INTERFACE ROUTING OPTIONS................................................... 22 CONTROL INTERFACE OPERATION ........................................................................ 24 CONTROL INTERFACE TIMING ................................................................................ 27 MASTER CLOCK ........................................................................................................ 29 AUDIO SAMPLING RATES AND AUDIO INTERFACES ............................................. 30 AUDIO INTERFACE FORMATS.................................................................................. 35 DIGITAL AUDIO INTERFACE CONTROL REGISTERS ............................................. 38 POWERDOWN MODES ............................................................................................. 39 MASTER CLOCK AND PHASE LOCKED LOOP......................................................... 42 S/PDIF TRANSCEIVER FEATURES........................................................................... 45 S/PDIF TRANSMITTER............................................................................................... 47 S/PDIF RECEIVER...................................................................................................... 50 DAC CONTROL REGISTERS ..................................................................................... 56 OUTPUT SELECT AND ENABLE CONTROL ............................................................. 65 ADC CONTROL REGISTERS ..................................................................................... 66 LIMITER / AUTOMATIC LEVEL CONTROL (ALC) ...................................................... 68 SOFTWARE REGISTER RESET ................................................................................ 72
REGISTER MAP...................................................................................................73 DIGITAL FILTER CHARACTERISTICS ...............................................................95 DAC FILTER RESPONSES .................................................................................95 ADC HIGH PASS FILTER ....................................................................................96
DIGITAL DE-EMPHASIS CHARACTERISTICS........................................................... 97
APPLICATIONS INFORMATION .........................................................................98
EXTERNAL ANALOGUE INPUT CIRCUIT CONFIGURATION ................................... 98 EXTERNAL S/PDIF INPUT CIRCUIT CONFIGURATION ........................................... 99 RECOMMENDED ANALOGUE OUTPUT EXTERNAL COMPONENTS.................... 100
IMPORTANT NOTICE ........................................................................................102
ADDRESS: ................................................................................................................ 102
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WM8777
PIN CONFIGURATION
ORDERING INFORMATION
DEVICE WM8777SEFT/V TEMPERATURE RANGE -25oC to +85oC PACKAGE 100-pin TQFP MOISTURE SENSITIVITY LEVEL MSL3 PEAK SOLDERING TEMPERATURE 240C
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WM8777 PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NAME PGND PVDD CLKOUT PDATAOP PDATAIP1 PDATAIP2 PDATAIP3 PDATAIP4 PDATAIPLRC PDATAOPLRC PBCLK MCLK SDOUT DVDD DGND CSB SCLK SDIN AIN1L AIN1R AIN2L AIN2R AIN3L AIN3R AIN4L AIN4R AIN5L AIN5R AIN6L AIN6R AINOPL AINVGL AINVGR AINOPR RECL RECR AVDDADC REFADCP VMIDADC AGNDADC REFADCN DACREFP1 DACREFN1 VMIDDAC1 RAUXSOP RAUXBMIN LAUXSOP LAUXBMIN AUXR AUXL TYPE Supply Supply Digital output Digital output Digital Input Digital Input Digital Input Digital Input Digital input/output Digital input/output Digital input/output Digital input/output Digital output Supply Supply Digital input Digital input Digital input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Output Analogue Input Analogue Input Analogue Output Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Supply Supply Analogue output Analogue output Analogue input Analogue output Analogue input Analogue output Analogue output PLL ground supply PLL positive supply PLL output or crystal oscillator output Primary Audio Interface data output (ADC) Primary Audio Interface data input 1 (DAC1) Primary Audio Interface data input 2 (DAC2) Primary Audio Interface data input 3 (DAC3) Primary Audio Interface data input 4 (DAC4) DAC left/right word clock ADC left/right word clock ADC and DAC audio interface bit clock DESCRIPTION
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Master DAC and ADC clock; 128, 192, 256, 384, 512, 768fs or 1152fs (fs = word clock freq) Serial interface output data Digital positive supply Digital negative supply Serial interface Latch signal (5V tolerant) Serial interface clock (5V tolerant) Serial interface data (5V tolerant) Channel 1 left input multiplexor virtual ground Channel 1 right input multiplexor virtual ground Channel 2 left input multiplexor virtual ground Channel 2 right input multiplexor virtual ground Channel 3 left input multiplexor virtual ground Channel 3 right input multiplexor virtual ground Channel 4 left input multiplexor virtual ground Channel 4 right input multiplexor virtual ground Channel 5 left input multiplexor virtual ground Channel 5 right input multiplexor virtual ground Channel 6 left input multiplexor virtual ground Channel 6 right input multiplexor virtual ground Left channel multiplexor output Left channel multiplexor virtual ground Right channel multiplexor virtual ground Right channel multiplexor output Left channel input mux select output Right channel input mux select output Analogue positive supply for ADC ADC reference buffer decoupling pin; 10uF external decoupling ADC midrail divider decoupling pin; 10uF external decoupling Analogue negative supply and substrate connection for ADC ADC ground reference DAC positive reference supply DAC ground reference DAC midrail decoupling pin ; 10uF external decoupling Right aux/rear channel summer output Right Aux/rear channel bass managed filtered input Left aux/rear channel summer output Left Aux/rear channel bass managed filtered input DAC aux or rear channel right output DAC aux or rear channel left output
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Product Preview PIN 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NAME RRBMIN RSURSOP SURR LRBMIN LSURSOP SURL AUX3R AUX3L LFE LFEVE LFESUM LFESOP AVDDDAC AGNDDAC HPHONER HPHONEL AUX2R AUX2L CNTR CNTSOP CIN3 CIN2 CIN1 FRONTR RIN3 RIN2 RIN1 RSUMOP FRONTL LIN3 LIN2 LIN1 LSUMOP AUX1R AUX1L VMIDDAC2 DACREFN2 DACREFP2 GPIO1 GPIO2 GPIO3 GPO/MODE SPIN SPDIFOP SPBCLK SLRC SDATAOP SDATAIP XTO XTI TYPE Analogue input Analogue output Analogue output Analogue input Analogue output Analogue output Analogue input Analogue input Analogue output Analogue Input Analogue output Analogue output Supply Supply Analogue output Analogue output Analogue input Analogue input Analogue output Analogue output Analogue input Analogue input Analogue input Analogue output Analogue input Analogue input Analogue input Analogue output Analogue output Analogue input Analogue input Analogue input Analogue output Analogue input Analogue input Analogue output Supply Supply Digital input/output Digital input/output Digital input/output Digital input/output Digital input Digital output Digital input/output Digital input/output Digital output Digital Input Crystal op Digital input DESCRIPTION Right surround channel bass managed filtered input Right surround channel summer output DAC surround channel right output Left surround channel bass managed filtered input Left surround channel summer output DAC surround channel left output 3.1 Multiplexor channel 3 right virtual ground input 3.1 Multiplexor channel 3 left virtual ground input DAC LFE channel right output LFE channel summer virtual earth LFE channel summer output LFE channel summer output Analogue positive supply for DAC
WM8777
Analogue negative supply and substrate connection for DAC Headphone channel right output headphone channel left output 3.1 Multiplexor channel 2 right virtual ground input 3.1 Multiplexor channel 2 left virtual ground input DAC centre channel right output Centre front channel summer output Centre channel bass management filter input Centre channel bass filter input Centre channel treble filter input DAC front channel right output Right front channel bass management filter input Right front channel bass filter input Right front channel treble filter input Right front channel summer output DAC front channel left output Left front channel bass management filter input Left front channel bass filter input Left front channel treble filter input Left front channel summer output 3.1 Multiplexor channel 1 right virtual ground input 3.1 Multiplexor channel 1 left virtual ground input DAC midrail decoupling pin ; 10uF external decoupling DAC ground reference DAC positive reference supply Selectable i/o (S/PDIF input, status flag output or ADCMCLK) Selectable i/o (S/PDIF input, status flag output, or PDATAOPBCLK) Selectable i/o (S/PDIF input or status flag output) Selectable i/o (state at RESET determines control interface type) S/PDIF input S/PDIF output Secondary Audio Interface bit clock Secondary Audio Interface left/right clock Secondary Audio Interface output data Secondary Audio Interface input data Crystal oscillator output Crystal oscillator or external clock inputs
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WM8777 ABSOLUTE MAXIMUM RATINGS
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Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per specification IPC/JEDEC J-STD-020B, this product requires specific storage conditions prior to surface mount assembly. It has a Moisture Sensitivity Level of 3 and as such will be supplied in vacuum-sealed moisture barrier bags, with an out of bag exposure time limit of 1 week at less than 30C / 60% RH. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs (SDIN, SCLK, CSB) Voltage range digital inputs (MCLK, DIN[3:0], PDATAOPLRC, PDATAIPLRC and PBCLK) Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature Note: 1. Analogue and digital grounds must always be within 0.3V of each other. -25C -65C MIN -0.3V -0.3V DGND -0.3V DGND -0.3V AGND -0.3V MAX +3.63V +7V +7V DVDD + 0.3V AVDD +0.3V 37MHz +85C +150C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue supply range Analogue Reference range Ground SYMBOL DVDD AVDDDAC,AVDDACD, PVDD VREFP AGNDDAC, AGNDADC, PGND, DGND, VREFN -0.3 TEST CONDITIONS MIN 2.7 4.5 4.5 0 TYP MAX 3.6 5.5 5.5 V UNIT V V
Difference DGND to AGNDDAC/AGNDADC/PLL GND
0
+0.3
V
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WM8777
ELECTRICAL CHARACTERISTICS
Test Conditions AVDDDAC = 5V, AVDDADC=5V, DVDD = 3.3V, AGNDDAC = 0V, AGNDADC = 0, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER Input LOW level Input HIGH level Input Leakage Current Input Capacitance Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance VVMID (DAC) VVMID (ADC) RVMID (DAC) RVMID (ADC) VREFP to VMID and VMID to VREFN AVDDADC to VMID and VMID to AGNDADC VREFP/2 AVDDADC/2 50k 50k V V VOL VOH IOL=1mA IOH-1mA 0.9 x DVDD SYMBOL VIL VIH 0.7 X DVDD 0.2 5 0.1 x DVDD TEST CONDITIONS MIN TYP MAX 0.3 X DVDD UNIT V V A pF V V Digital Logic Levels ( CMOS Levels)
DAC Performance (Load = 10k , 50pF) to pins L/RSUMOP, CNTSOP, LFESOP, L/RSUROP, L/RAUXSOP 0dBFs Full scale output voltage SNR (Note 1,2) SNR (Note 1,2) Dynamic Range (Note 2) Total Harmonic Distortion (THD) DAC channel separation DAC Mute attenuation Power Supply Rejection Ratio PSRR 1KHz Input, 0dB gain 1kHz 100mVpp 20Hz to 20kHz 100mVpp DAC Digital Volume DAC Digital volume control range DAC Digital volume step size ADC Performance Input Signal Level (0dB) SNR (Note 1,2) SNR (Note 1,2) Dynamic Range (note 2) Total Harmonic Distortion (THD) ADC Channel Separation Programmable Gain Step Size Programmable Gain Range (Analogue) Programmable Gain Range (Digital) Mute Attenuation Power Supply Rejection Ratio PSRR 1kHz Input 1kHz Input 1kHz Input, 0dB gain 1kHz 100mVpp -21 -103 82 50 A-weighted, 0dB gain @ fs = 48kHz A-weighted, 0dB gain @ fs = 96kHz A-weighted, -60dB full scale input 1kHz, 0dBFs 1kHz, -1dBFs 1kHz Input 93 1.0 x AVDDADC/5 102 100 102 -89 -94 85 0.5 +24 -21.5 -85 Vrms dB dB dB dB dB dB dB dB dB dB dB PP Rev 1.94 November 2004 7 -127.5 0.5 0 dB dB DNR A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted, -60dB full scale input 1kHz, 0dBFs 100 100 1.0 x VREFP/5 108 108 108 -94 110 100 50 45 -90 Vrms dB dB dB dB dB dB dB dB
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WM8777
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Test Conditions AVDDDAC = 5V, AVDDADC=5V, DVDD = 3.3V, AGNDDAC = 0V, AGNDADC = 0, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS 20Hz to 20kHz 100mVpp Input Resistance (AIN1 -> AIN6) Input Capacitance (AIN1 -> AIN6) MIN TYP 45 20 10 MAX UNIT dB k pF
ADC PGA Output to Analogue Output (L/RSUMOP, CNTSOP, LFESOP, L/RSUROP, L/RAUXSOP) (Load=10k , 50pF, gain = 0dB) Bypass Mode 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio Mute Attenuation 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio Mute Attenuation ADC PGA to REC Output 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio Mute Attenuation L/RSUMOP to REC Output 0dB Full scale output voltage SNR (Note 1) THD Power Supply Rejection Ratio Mute Attenuation Analogue output Volume Gain Step Size Analogue output Volume Gain Range Analogue output Volume Mute Attenuation Analogue Tone volume step size 1kHz Input 1kHz Input, 0dB gain PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mV 1kHz, 0dB 0.5 -100 100 1 90 1.0 x AVDDDAC/5 104 -93 -95 50 45 100 1 1.5 +20 Vrms dB dB dB dB dB dB dB dB dB dB PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mV 1kHz, 0dB 90 1.0 x AVDDDAC/5 104 -93 -95 50 45 100 Vrms dB dB dB dB dB dB PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mV 1kHz, 0dB 90 PSRR 1kHz, 0dB 1kHz, -3dB 1kHz 100mVpp 20Hz to 20kHz 100mV 1kHz, 0dB 90 1.0 x AVDDDAC/5 104 -93 -95 50 45 100 1.0 x AVDDDAC/5 104 -93 -95 50 45 100 Vrms dB dB dB dB dB dB Vrms dB dB dB dB dB dB
Analogue Input (AIN6) to Analogue Output (FRONTL, FRONTR) (Load=10k , 50pF, gain = 0dB) Bypass Mode
Volume Controls (FRONTL, FRONTR, CNTR, LFE, SURR, SURL, AUXL, AUXR, HPHONER, HPHONEL, LFESUM)
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WM8777
Test Conditions AVDDDAC = 5V, AVDDADC=5V, DVDD = 3.3V, AGNDDAC = 0V, AGNDADC = 0, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER Treble range adjustment Treble step size Bass range adjustment Bass step size Headphone Amplifier at 0dB Volume (Load=16 , at 1Vrms) Headphone output level THD SNR Headphone Amplifier at 0dB Volume (Load=32 , at 1Vrms) Headphone output level THD SNR S/PDIF Transceiver Jitter on recovered clock (Rms period jitter) S/PDIF Input Levels CMOS MODE Input LOW level Input HIGH level Input capacitance Input Frequency S/PDIF Input Levels Comparator MODE Input capacitance Input resistance Input frequency Input Amplitude PLL Period Jiffer XTAL Input XTI LOW level Input XTI HIGH level Input XTI capacitance Input XTI leakage Output XTO LOW Output XTO HIGH Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). VXIL VXIH CXJ IXleak VXOL VXOH 15pF load capacitors 15pF load capacitors 0 853 3.32 28.92 86 1.458 4.491 38.96 278 1.942 557 mV mV pF mA mV V 80 ps(rms) 200 1.31 18 25 0.5 X DVDD pF MHz mV VIL VIH 0.7 X DVDD 1.25 36 0.3 X DVDD V V pF MHz 50 Ps 0.95 -68 -100 Vrms dB dB 1.5 -74 -96 Vrms dB dB -10 1 SYMBOL TEST CONDITIONS MIN -10 1 +10 TYP MAX +10 UNIT dB dB dB dB Analogue Bass Management and Tone Controls
3.
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WM8777
TERMINOLOGY
1. 2.
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Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
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WM8777
SUPPLY CURRENT
The supply current of the WM877 depends on the operating mode. For example, the supply current is lower when the device is used for playback-only (ADC off) or recording-only (DACs off). The supply currents for various operating modes are shown in Table 1 below.
MODE DESCRIPTION AVDDDAC On power-up, no clks applied On power-up, clks applied ADC All DACs ADC, All DACs ADC, All DACs, Osc ADC, All DACs, Osc, PLL ADC, All DACs, Osc, PLL, S/PDIF ADC, All DACs, Osc, PLL, S/PDIF, Tone ADC, All DACs, Osc, PLL, S/PDIF, Tone, HP (16 Ohm) Power-down, no clks applied Power-down, clks applied Software RESET Table 1 Supply Current for Functional Blocks Notes: 1. 2. 3. 4. DAC Analogue supply (AVDDDAC) = 5V. ADC Analogue supply (AVDDADC) = 5V. PLL Analogue supply (PVDD) = 5V. Digital supply (DVDD) = 3.3V. 2.81 2.81 2.71 55.35 53.45 53.44 53.38 53.38 87.53 146.60 0.028 0.028 2.80 1.89 1.89 38.86 1.90 38.69 38.70 38.62 38.62 38.53 38.42 0.172 0.172 1.88
SUPPLY CURRENT AVDDADC PVDD 0.30 0.30 0.30 0.30 0.30 1.12 3.74 3.43 3.43 3.44 0.30 0.30 0.3 DVDD 0.39 1.70 5.80 18.61 22.4 22.4 28.65 29.89 29.99 29.99 0.39 1.60 0.95 TOTAL 5.39 6.70 47.67 76.16 114.84 115.66 124.39 125.32 159.48 218.45 0.89 2.10 5.93 UNIT mA mA mA mA mA mA mA mA mA mA mA mA mA
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WM8777 DEVICE DESCRIPTION
INTRODUCTION
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WM8777 is a complete 8-channel DAC, 2-channel ADC audio codec, with integrated S/PDIF transceiver, analogue tone controls and bass management including analogue volume controls on each channel. The device is implemented as four separate stereo DACs and a stereo ADC with flexible input multiplexer, in a single package and controlled by a single interface. The four stereo channels may either be used to implement a 5.1 channel surround system, with additional stereo channel for a stereo mix down channel, or for a complete 7.1 channel surround system. An analogue bypass path option is available, to allow stereo analogue signals from any of the 8 stereo inputs to be sent to the stereo outputs via the main volume controls. This allows a purely analogue input to analogue output high quality signal path to be implemented if required. This would allow, for example, the user to play back a 5.1 channel surround movie through 6 of the DACs, whilst playing back a separate analogue or digital signal into a remote room installation. The WM8777 has two digital audio interfaces. The primary audio interface has separate inputs for each stereo DAC, and one data output which can output digital data from the ADC, received S/PDIF data or data received from the secondary audio interface. Data directed to DAC1 is also directed to the S/PDIF transmitter. The secondary audio interface has a single data input and a single data output. The input data can be output over the primary audio interface, or converted into S/PDIF format and output over the S/PDIF transmitter. Both audio interfaces may be configured to operate in either master or slave mode and support right justified, left justified and I2S interface formats along with a highly flexible DSP serial port interface. The input multiplexor to the ADC is configured to allow large signal levels to be input to the ADC, using external resistors to reduce the amplitude of larger signals to within the normal operating range of the ADC. The ADC input PGA also allows input signals to be gained up to +24dB and attenuated down to -21dB. This allows the user maximum flexibility in the use of the ADC. A selectable stereo record output is also provided on RECL/R. It is intended that the RECL/R outputs are only used to drive a high impedance buffer. Each DAC has its own digital volume control. The digital volume control changes can be made in 0.5dB steps. In addition a zero cross detect circuit is provided for each DAC. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. In addition to this there is an analogue volume control on each of the tone outputs, with a zero cross detect circuit. The analogue volume control changes can be made in 1dB steps. When analogue volume zero-cross detection is enabled the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. Additionally, 6 of the DAC outputs incorporate an input selector and mixer allowing an external 6 channel, or 5.1 channel signal, to be either switched into the signal path in place of the DAC signal or mixed with the DAC signal. Control of internal functionality of the device is by 3-wire SPI or 2-wire serial control interface selectable by the state of the GPO/MODE pin on power up. The control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. CSB, SCLK, and SDIN are 5V tolerant with TTL input thresholds, allowing the WM8777 to be used with DVDD = 3.3V and be controlled by a controller with 5V output. Operation using a system clock of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. In Slave mode selection between clock rates is automatically controlled. In master mode the master clock to sample rate ratio is set by control bits PAIFTX_RATE and PAIFRX_RATE. The ADC and DAC may run at different rates within the constraint of a common master clock. For example with master clock at 24.576MHz, a DAC sample rate of 96kHz (256fs mode) and an ADC sample rate of 48kHz (512fs mode) can be accommodated. Sample rates (fs) from less than 8ks/s up to 192ks/s are allowed, provided the appropriate system clock is input.
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WM8777
ANALOGUE TONE CONTROLS
Facilities are provided for implementation of analogue treble and bass tone controls on each of the Front left, right and centre channels. External R and C values are used to set the corner frequencies of these tone control functions, allowing the system builder to choose the required responses. Adjustment of the amplitude of the required tone response is made electronically by writing the required gain or attenuation value into the WM8777 over the serial control interface. Maximum boost or attenuation of tone control values of +/-10dB in 1dB steps is provided. A tone control bypass path is provided, plus input summing paths for Rear (i.e. Surround L/R), Centre and LFE channels, to allow for creation of a stereo `mix-down' signal when only two speakers are supported. Each of these mix-down paths has independent gain adjust from 0dB to -6db in 1dB steps. An analogue input bypass path is also provided. This allows AIN6L and AIN6R to be output on the FRONTL and FRONTR output channels making use of the volume controls if required. In order to provide sufficient headroom for cases where significant amounts of analogue treble or bass boost have been applied, a gain attenuation control is provided in the summing stage after the tone adjust PGAs. This allows attenuation of -6dB, -12dB or -18dB to be applied. Re-adjustment of the nominal 0dB signal level may then be made in the following volume control stage as required.
Stereo Mix-down inputs AIN6L/R RearL/R Center LFE
No-Sub Option
Tone Control Bypass pad Bass management filter DAC Bass filter Bypass Aux input pad XSUMOP XIN1 pad +/-10dB XIN2 pad Bass cut pad Treble boost FRONTL/R Treble cut Treble filter Bass Managed Signal 0 to -6dB 0, -6, -12, -18dB Bass boost Main Volume Control +20dB to -100dB
XIN3
Bass Management
Figure 1 Tone Control Configuration - Front Left/Right (single channel shown)
No-Sub Option
LFE 0 to -6dB
To Front L/R
Tone Control Bypass pad Bass management filter DAC Bass filter Bypass Aux input pad CNTSUMOP CIN1 pad CIN2 pad Bass cut Bass Managed Signal
CIN3 Bass boost
0, -6, -12, -18dB
Main Volume Control +20dB to -100dB
pad Treble boost CNTR Treble cut
Treble filter
+/-10dB
Bass Management
Figure 2 Tone Control Configuration - Centre Channel
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WM8777
MIXER CONTROL
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Control of the front channel signal paths is via five software registers. The first three registers control both the front left and right channels whilst the remaining two control the centre channel. When only two speakers are available a stereo mix-down signal can be created by setting the REAR, CNTR and LFE bits of the appropriate register. Control of the tone characteristics for a channel is determined by writing to the XTRBL and XBASS register bits (where X implies either Front L/R or Centre channel). The tone controls work by adding/subtracting high/low-pass filtered signal content to the nominal 0dB bass-managed signal. Thus when using the tone controls, the XBM bit should also be set. Note also that cut and boost cannot be applied simultaneously. If both bits are set, the tone control signal path will be bypassed but the amplifiers will remain enabled. To avoid pop-noises during dynamic tone control it is recommending that this method is used to disable the tone control signal path. Setting both bits low disables the path, however it will also cause the amplifiers to power down. The mixer control registers (FTRBL, FBASS, CTRBL and CBASS) share the zero-cross detect circuit used by the analogue volume control. Thus the ZCEN enable bit for a particular channel can be used to determine whether or not the tone control signal path select signals are updated only on a zerocross condition. The bypass path is selected by setting the FBYP bit for the front L/R channels and the CBYP bit for the centre channel. The centre, rear and LFE channels can all be independently summed into the front L/R channels by setting the CNTR, REAR and FLFE bits respectively. Each of these signal paths has independent gain control from 0 to -6dB, adjustable in 1dB steps. These gains are determined by writing to the attenuation registers CNTRGAIN, REARGAIN and FLFEGAIN respectively. The LFE channel can also be summed into the front centre channel by setting the CLFE bit. This path also has independent gain control from 0 to -6dB, controlled by writing to the CLFEGAIN register. REGISTER ADDRESS (22h) FRONT Mixer Control 1 BIT 1:0 LABEL FTRBL[1:0] DEFAULT 00 DESCRIPTION Control treble boost and cut:00 = both off ( Amps disabled) 01 = Treble cut 10 = Treble boosted 11 = both off (Amps enabled) Controls bass boost and cut:00 = both off (Amps disabled) 01 = Bass cut 10 = Bass boosted 11 = both off (Amps enabled) Bass Managed Signal path select 0 = Open 1 = Closed Tone Control Bypass signal path select 0 = Open 1 = Closed 0 = AIN6 not selected 1 = AIN6 applied to FRONT channels Front LFE gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB
3:2
FBASS[1:0]
00
4
FBM
0
5
FBYP
0
6
AIN6
0
(23h) FRONT Mixer Control 2
2:0
FLFEGAIN[2:0]
000
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Product Preview REGISTER ADDRESS BIT 3 LABEL FLFE DEFAULT 0 DESCRIPTION
WM8777
LFE signal path select 0 = Open 1 = Closed Front CNTR gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB Centre signal path mix 0 = Open 1 = Closed Front REAR gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB Rear signal path mix Control treble boost and cut: 00 = both off 01 = Treble cut 10 = Treble boosted 11 = both off Controls bass boost and cut:00 = both off 01 = Bass cut 10 = Bass boosted 11 = both off Bass Managed Signal path select 0 = Open 1 = Closed Tone Control Bypass signal path select 0 = Open 1 = Closed Center LFE gain:000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB LFE signal path select 0 = Open 1 = Closed
6:4
CNTRGAIN[2:0]
000
7
CNTR
0
(24h) FRONT Mixer Control 3
2:0
REARGAIN[2:0]
000
3 (25h) Center Mixer Control 1 1:0
REAR CTRBL[1:0]
0 00
3:2
CBASS[1:0]
00
4
CBM
0
5
CBYP
0
(26h) Center Mixer Control 2
2:0
CLFEGAIN[2:0]
000
3
CLFE
0
Table 2 Output Mixer Control Registers
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WM8777
TONE CONTROL GAIN
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The amplitude of the tone response is controlled by writing gain values to the appropriate gain registers. The front left and right channels share gain registers, whilst the centre channel may be controlled independently. Table 3 shows how the attenuation levels for the tone control blocks are selected from the 4-bit code words. The tone control attenuation registers share the zero-cross detect circuit used by the analogue volume control. Thus the ZCEN enable bit for a particular channel can be used to determine whether or not the treble/bass attenuation registers for that channel are updated only on a zero-cross condition. CUT/BOOST CODE[3:0] 0000 0001 BOOST . . 1001 0000 0001 CUT . . 1001 Table 3 Tone Control Attenuation Levels ATTENUATION LEVEL +1dB +2dB . . +10dB -1dB -2dB . . -10dB
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WM8777
REGISTER ADDRESS (28h) Front Bass Control BIT 3:0 8 LABEL FBASS[3:0] UPDATE DEFAULT 0000 Not latched DESCRIPTION Gain control for Bass boost/cut Controls simultaneous update of all Attenuation Latches 0 = Store GAIN FRONT BASS in intermediate latch (no change to output) 1 = Store GAIN FRONT BASS and update attenuation on all channels. Gain control for Bass boost/cut Controls simultaneous update of all Attenuation Latches 0 = Store GAIN FRONT TREBLE in intermediate latch (no change to output) 1 = Store GAIN FRONT TREBLE and update attenuation on all channels. Gain control for Bass boost/cut Controls simultaneous update of all Attenuation Latches 0 = Store GAIN CENTER BASS in intermediate latch (no change to output) 1 = Store GAIN CENTER BASS and update attenuation on all channels. Gain control for Bass boost/cut Controls simultaneous update of all Attenuation Latches 0 = Store GAIN CENTER TREBLE in intermediate latch (no change to output) 1 = Store GAIN CENTER TREBLE and update attenuation on all channels.
(29h) Front Treble Control
3:0 8
FTREB[3:0] UPDATE
0000 Not latched
(2Ah) Center Bass Control
3:0 8
CBASS[3:0] UPDATE
0000 Not latched
(2Bh) Center Treble Control
3:0 8
CTREB[3:0] UPDATE
0000 Not latched
Table 4 Tone Control Gain Registers
TONE CONTROL PRE-GAIN The tone pre-gain is applied directly before the analogue volume control for a channel. This is to allow scaling of the channel response prior to the overall channel volume control. Each of the front right, left and centre channels accept their own 2-bit gain code to determine to amount of attenuation applied. The Attenuation levels are given in Table 5. PRE-GAIN[0:1] 00 01 10 11 ATTENUATION 0dB -6dB -12dB -18dB
Table 5 Tone Control Pre-Gain Attenuation
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WM8777
REGISTER ADDRESS (2Ch) Mixer Pregain BIT 1:0 LABEL CNTP[1:0] DEFAULT 00 DESCRIPTION
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PREGAIN control for CNTR control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation PREGAIN control for FRONTR tone control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation PREGAIN control for FRONTL tone control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN CNTR in intermediate latch (no change to output) 1 = Store PREGAIN CNTR and update attenuation on all channels. Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN RIGHT in intermediate latch (no change to output) 1 = Store PREGAIN RIGHT and update attenuation on all channels. Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN LEFT in intermediate latch (no change to output) 1 = Store PREGAIN LEFT and update attenuation on all channels.
3:2
FTRP[1:0]
00
5:4
FTLP[1:0]
00
6
UPDATEC
0
7
UPDATER
0
8
UPDATEL
0
Table 6 Mixer Pre-Gain Registers
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WM8777
BASS MANAGEMENT
Support is provided for Bass Management in the analogue domain. This might be used either in the case where a partnering DSP has insufficient MIPs to support all required functions, or where an analogue multi-channel input is required to be processed for use with `small' bass-limited speakers. Provision is made for single pole high pass filtering of each front, centre, surround or rear channel, using a single external capacitor. The value of this capacitor may be chosen to set the required highpass corner frequency, typically the Dolby recommended 100Hz value being preferred. Use of extra external FET switches would allow the system builder to adjust this corner frequency in the system. To create the subwoofer channel signal, each of up to all 6 channels is summed into the LFE channel using external discrete summing resistors, and the entire summed subwoofer signal then low-pass band-limited using a further user selectable external capacitor value. This allows the gain from each individual channel, and the overall bass corner response to be selected. Following this summing stage, an integrated volume control allows the overall level of the subwoofer channel to be set.
To front left tone network
DAC Bypass AUX DAC Bypass AUX DAC Bypass AUX DAC Bypass AUX DAC Bypass AUX DAC Bypass AUX DAC Bypass
LSUMOP
LFEVE PAD
+20dB to -100dB
+
PAD
To front right tone network
RSUMOP
PAD LFE
To centre tone network
+
PAD
CNTSOP
LFESUM PAD
100Hz Lowpass
+
PAD
LFESOP
+
PAD To front channels
LSUROP
LRBMIN PAD
100Hz Highpass
+
PAD
+20dB to -100dB
PAD RRBMIN
+20dB to -100dB
RSUROP
SURL PAD
+
PAD
PAD
100Hz Highpass
LAUXOP
LAUXBMIN PAD
100Hz Highpass (or 10Hz if no bass management)
+
PAD
+20dB to -100dB
SURR PAD
DAC Bypass
RAUXSOP
RAUXBMIN PAD
100Hz Highpass (or 10Hz if no bass management)
+
PAD
+20dB to -100dB
AUXL PAD AUXR
Figure 3 Bass Management Configuration
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WM8777
BASS MANAGEMENT BYPASS
Product Preview
Signal paths are provided for the surround and auxiliary channels which allow the user to bypass the high pass filtering operation and apply the unfiltered signals directly to the analogue volume controls. REGISTER ADDRESS (27h) Bass Management Bypass BIT 0 LABEL AUXLBYP DEFAULT 0 DESCRIPTION Bypass select for AUX left output 0 = Bass managed 1 = Bypass Bypass select for AUX right output 0 = Bass managed 1 = Bypass Bypass select for surround left output 0 = Bass managed 1 = Bypass Bypass select for surround right output 0 = Bass managed 1 = Bypass
1
AUXRBYP
0
2
SURLBYP
0
3
SURRBYP
0
Table 7 Bass Management Bypass Register
HEADPHONE OUTPUT
A stereo headphone output is provided which may be used to buffer out either the front L/R channels, or the AUX L/R channels as required. Control is via the HPSEL bit. An independent volume control is provided for this output. REGISTER ADDRESS (25h) Centre Mixer Control 1 BIT 6 LABEL HPSEL DEFAULT 0 DESCRIPTION Controls headphone output MUX:0 = FRONT L/R output on headphone channels 1 = AUX L/R output on headphone channels
Table 8 Headphone Source Select
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Product Preview
WM8777
OUTPUT POWERDOWN
The analogue output signal paths are all disabled by default and can be controlled by writing to the appropriate software control register. REGISTER ADDRESS (2Dh) Output Powerdown BIT 0 LABEL AUXLPD DEFAULT 1 DESCRIPTION Auxiliary left output powerdown. 0 = enabled 1 = disabled Auxiliary right output powerdown. 0 = enabled 1 = disabled Surround left output powerdown. 0 = enabled 1 = disabled Surround Right output powerdown. 0 = enabled 1 = disabled LFE output powerdown. 0 = enabled 1 = disabled Center output powerdown. 0 = enabled 1 = disabled Front Left output powerdown. 0 = enabled 1 = disabled Front Right output powerdown. 0 = enabled 1 = disabled Headphone output powerdown. 0 = enabled 1 = disabled
1
AUXRPD
1
2
SURLPD
1
3
SURRPD
1
4
LFEPD
1
5
CTRPD
1
6
FRTLPD
1
7
FRTRPD
1
8
HPPD
1
Table 9 Output Powerdown Register
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WM8777
DIGITAL AUDIO INTERFACE ROUTING OPTIONS
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The WM8777 has extremely flexible digital audio interface routing options which are illustrated in Figure 4. It has an S/PDIF receiver, S/PDIF transmitter and two digital audio interfaces. Each DAC has its own digital input pin PDATAIP1/2/3/4. Internal multiplexors in the primary audio interface (DAC) allow the data received on any DIN pin to be routed to any DAC .Any DIN pin routed to DAC1 is also routed to the S/PDIF and Secondary Audio Interface transmitters. DAC1 may also be used to convert received S/PDIF data to analogue, while DACs 2-4 take data only from the primary audio interface. The primary audio interface can output ADC data, received S/PDIF data or data from the secondary audio interface on the PDATAOP pin. The secondary audio interface can output ADC data, received S/PDIF data and data received through PDATAIP1-4 on the SDATAOP pin. The S/PDIF transmitter can output S/PDIF received data, and converts ADC data and data from both audio interfaces into S/PDIF format and outputs them on SPDIFOP.
Figure 4 WM8777 Digital Routing Diagram
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Product Preview REGISTER ADDRESS R65 (41h) Interface Source Select BIT 0 LABEL RX2DAC DEFAULT 0 DESCRIPTION
WM8777
Received S/PDIF PCM data to DAC. 0 = DAC1 takes data from Primary Audio Interface. 1 = DAC1 takes data from S/PDIF receiver. Note: If DACs 2, 3 and 4 are disabled, DAC1 uses the subframe rate of the S/PDIF input with respect to any selected MCLK. PLL clock should be selected to set the fs mode. If DAC 2, 3 or 4 are enabled, the user must ensure that DACLRC and the S/PDIF subframe are operating at the same rate; any difference will cause a sample slip on DAC1.
2:1
TXSRC[1:0]
00
S/PDIF Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Secondary Audio Interface received data 11 = DAC Audio Interface Received data. Note: The output rate is determined by the source of the data to be transmitted. The ADC outputs S/PDIF at a rate determined by LRCLK. Audio Interface output source 00 = S/PDIF received data 01 = ADC digital output data 10 = Secondary Audio Interface received data 11 = Power-down Primary Audio Interface Transmitter Note: for cases 00 and 10, the user must ensure that the source rate matches the transmit rate; any difference will cause samples to be lost. For optimum performance, the PAIF should be operated in master mode, with the master clock source the same as the PAIF source.
5:4
PAIFSRC[1:0]
01
7:6
SAIFSRC[1:0]
00
Secondary Audio Interface Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Power-down Secondary Audio Interface Transmitter 11 = Primary Audio Interface received data. Note: for cases 00 and 10, the user must ensure that the source rate matches the transmit rate; any difference will cause samples to be lost. For case 01, if PAIFSRC is not also 01, the ADC operation rate is set by the SLRC and ADCCLKSRC/PLL2ADC register bits.
Table 10 Interface Output Selection Register
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WM8777
CONTROL INTERFACE OPERATION
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The WM8777 is controlled using a 2-wire (plus readback pin) or 3-wire (plus readback pin) SPI compatible serial interface. The interface configuration is determined by the state of the GPIO/MODE pin on power up. If the GPIO/MODE pin is low while the power on reset is being applied internally, the 2-wire configuration is selected. If GPIO/MODE is high while the power on reset is being applied internally, the 3-wire configuration is selected - see table 11. The control interface is 5V tolerant, meaning that the control interface input signals CSB, SCLK and SDIN may have an input high level of 5V while DVDD is 3V. Input thresholds are determined by DVDD. GPIO/MODE AT POWER UP Low High CONTROL 2-wire 3-wire
Table 11 Control Interface Selection
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE WITH ADDITIONAL READBACK PIN
SDIN is used for the program data, SCLK is used to clock in the program data and CSB is used to latch the program data. SDIN is sampled on the rising edge of SCLK. The 2-wire interface protocol with readback is shown in Figure 5.
Figure 5 3 Wire SPI Compatible Interface 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits CSB is edge sensitive - the data is latched on the rising edge of CSB.
3-WIRE REGISTER READBACK
The read-only registers in the S/PDIF section can be read back via the SDOUT pin. To enable readback the READEN3 bit must be set. REGISTER ADDRESS (4Ah) Read-back Control BIT 4 LABEL READEN3 DEFAULT 0 DESCRIPTION 3-Wire Read-back mode enable. 0 = 3-Wire read-back mode disabled 1 = 3-Wire read-back mode enabled 2-Wire Read-back mode enable. 0 = 2-Wire read-back mode disabled 1 = 2-Wire read-back mode enabled
5
READEN2
0
Table 12 Readback Control Register The 3-wire interface readback protocol is shown in Figure 6. Note that the SDOUT pin is tri-state unless CSB is held low, therefore CSB must be held low for the duration of the read.
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Product Preview
WM8777
Figure 6 3-Wire SPI Compatible Control Interface Readback
2-WIRE SERIAL CONTROL MODE WITH ADDITIONAL READBACK PIN
The WM8777 supports software control via a 2-wire (plus readback pin) serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address of each register in the WM8777). The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8777, the WM8777 responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised, the WM8777 returns to the idle condition and wait for a new start condition and valid address. Once the WM8777 has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8777 register address plus the first bit of register data). The WM8777 then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8777 acknowledges again by pulling SDIN low. The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high. After receiving a complete address and data sequence the WM8777 returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
START
STOP
SCLK SDIN
address
in
wr
ack
out
B15-B8
in
ack
out
B7-B0
in
ack
out
device address [wr=0]
register address and 1st data bit
remaining data bits
Figure 7 2-Wire Serial Control Interface The WM8777 has two possible device addresses, which can be selected using the CSBpin. CSBSTATE Low or Unconnected High DEVICE ADDRESS IN 2WIRE MODE 0011010 0011011
Table 13 2-Wire MPU Interface Address Selection
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WM8777
2-WIRE SERIAL READBACK
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The WM8777 allows readback of certain registers in 2-wire mode, with data output on the SDOUT pin. Readback is set by writing to the Readback Control register (see Table 12) to set READEN2 to 1.
Figure 8 2-Wire Readback
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Product Preview
WM8777
CONTROL INTERFACE TIMING - 3-WIRE MODE
Figure 9 SPI Compatible Control Interface Input Timing Test Conditions DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER SCLK rising edge to CSBrising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising Table 14 SCLK Timing Requirements SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
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WM8777
CONTROL INTERFACE TIMING - 2-WIRE MODE
t
3
Product Preview
t
t
5
3
SDIN
t t t t
6
2
4
8
SCLK
t t
1
t
9
7
Figure 10 Control Interface Timing - 2-Wire Serial Control Mode (MODE=0) Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed Table 15 2-wire Control Interface Timing Information. t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 600 1.3 600 600 100 300 300 400 kHz ns us ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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Product Preview
WM8777
MASTER CLOCK
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the MCLK input pin with no software configuration necessary. In a system where there are a number of possible sources for the reference clock it is recommended that the clock source with the lowest jitter be used to optimise the performance of the ADC and DAC.
MASTER CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKP
Figure 11 Master Clock Timing Requirements Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER System Clock Timing Information
MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle
SYMBOL tMCLKH tMCLKL tMCLKP
TEST CONDITIONS
MIN 11 11 28 40:60
TYP
MAX
UNIT ns ns ns
60:40
Table 16 Master Clock Timing Requirements The master clock for WM8777 supports DAC and ADC audio sampling rates from 128fs to 1152fs, where fs is the audio sampling frequency (PDATAIPLRC or PDATAOPLRC) typically 32kHz, 44.1kHz, 48kHz, 96kHz, or 192KHz. The master clock is used to operate the digital filters and the noise shaping circuits. The WM8777 has a master clock detection circuit that automatically determines the relationship between the master clock frequency and the sampling rate (to within +/- 32 system clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available, 1152fs. The master clock must be synchronised with PDATAOPLRC/PDATAIPLRC, although the WM8777 is tolerant of phase variations or jitter on this clock.
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WM8777
AUDIO SAMPLING RATES AND AUDIO INTERFACES
DIGITAL AUDIO INTERFACES
Product Preview
The WM8777 has two audio interfaces - a primary audio interface and a secondary audio interface. The primary audio interface has four data inputs (PDATAIP1/2/3/4), one data output (PDATAOP), and is controlled by PBCLK, PDATAOPLRC and PDATAIPLRC clock pins. The secondary audio interface has one input (SDATAIP), one output (SDATAOP) and is controlled by SPBCLK and SLRC clock pins. Both audio interfaces operate in either Slave or Master mode, selectable using the PAIFRX_MS and SMS control bits. In both Master and Slave modes PDATAIP1/2/3/4 and SDATAIP are always inputs to the WM8777 and PDATAOP and SDATAOP are always outputs. The default is Slave mode.
SLAVE MODE
In Slave mode (PAIFRX_MS/SMS=0) PDATAOPLRC, PDATAIPLRC, SLRC, PBCLK and SPBCLK are inputs to the WM8777. PDATAIP1/2/3/4, PDATAOPLRC and PDATAIPLRC are sampled by the WM8777 on the rising edge of PBCLK. SDATAIP and SLRC are sampled by the WM8777 on the rising edge of SBCLK. Data output PDATAOP changes on the falling edge of PBCLK and data output on SDATAOP changes on the falling edge of SBCLK. By setting control bit PAIFRX_BCP the polarity of PBCLK may be reversed so that PDATAIP1/2/3/4, PDATAOPLRC and PDATAIPLRC are sampled on the falling edge of PBCLK and PDATAOP changes on the rising edge of PBCLK. Similarly the polarity of SBCLK can be reversed using control bit SBCP.
Figure 12 Digital Audio Interface - Slave Mode
Figure 13 Digital Audio Data Timing - Slave Mode
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Product Preview
WM8777
Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER PBCLK cycle time PBCLK pulse width high PBCLK pulse width low PDATAIPLRC/PDATAOPL RC set-up time to PBCLK rising edge PDATAIPLRC/PDATAOPL RC hold time from PBCLK rising edge PDATAIP1/2/3/4 set-up time to PBCLK rising edge PDATAIP1/2/3/4 hold time from PBCLK rising edge PDATAOP propagation delay from PBCLK falling edge SYMBOL tBCY tBCH tBCL tLRSU TEST CONDITIONS MIN 50 20 20 10 TYP MAX UNIT ns ns ns ns
Audio Data Input Timing Information
tLRH
10
ns
tDS tDH tDD
10 10 0 10
ns ns ns
Table 17 Digital Audio Data Timing - Slave Mode Note: PDATAOPLRC and PDATAIPLRC should be synchronous with MCLK, although the WM8777 interface is tolerant of phase variations or jitter on these signals.
The DACs support system clock to sampling clock ratios of 256fs to 1152fs when the DAC signal processing of the WM8777 is programmed to operate at 128 times oversampling rate (DACOSR=0). The DACs support ratios of 128fs and 192fs when the WM8777 is programmed to operate at 64 times oversampling rate (DACOSR=1). The ADC supports system clock to sampling clock ratios of 128fs to 1152fs. The signal processing for the WM8777 ADC typically operates at an oversampling rate of 128fs. For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate from 128fs to 64fs. For ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate from 64fs to 32fs. Table 18 shows the typical system clock frequencies for ADC operation at both 128 times oversampling rate (ADCOSR=0) and 64 times oversampling rate (ADCOSR=1), and DAC operation at 128 times oversampling rate (DACOSR=0). Table 19 shows typical system clock frequencies for ADC operation at 32/64 times oversampling rate (ADCOSR=1), and DAC operation at 64 times oversampling rate (DACOSR =1). SAMPLING RATE (PDATAIPLRC/ PDATAOPLRC) 32kHz 44.1kHz 48kHz 96kHz System Clock Frequency (MHz) 256fs 8.192 11.2896 12.288 24.576 384fs 12.288 16.9340 18.432 36.864 512fs 16.384 22.5792 24.576 768fs 24.576 33.8688 36.864 1152fs 36.864 Unavailable Unavailable
Unavailable Unavailable Unavailable
Table 18 ADC and DAC system clock frequencies versus sampling rate. (ADC operation at either 128 times oversampling rate (ADCOSR=0) or 64 times oversampling rate (ADCOSR=1), DAC operation at 128 times oversampling rate, DACOSR=0)
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WM8777
SAMPLING RATE (PDATAIPLRC/ PDATAOPLRC) 96kHz 192kHz System Clock Frequency (MHz) 128fs 12.288 24.576 192fs 18.432 36.864
Product Preview
Table 19 ADC and DAC system clock frequencies versus sampling rate. (ADC operation at 32/64 times oversampling rate (ADCOSR=1), DAC operation at 64 times oversampling rate (DACOSR=1)
MASTER MODE
In Master mode PBCLK, PDATAIPLRC, PDATAOPLRC, SLRC and SPBCLK are generated by the WM8777.
Figure 14 Audio Interface - Master Mode The frequencies of PDATAOPLRC, PDATAIPLRC and SLRC are set by setting the required ratio of MCLK to PDATAIPLRC, PDATAOPLRC and SLRC using the PAIFRX_RATE, PAIFTX_RATE and SAIFRATE control bits respectively, see Table 20. PAIFTX_RATE[2:0]/ PAIFRX_RATE[2:0] 000 001 010 011 100 101 110 MCLK : PDATAOPLRC/PDATAIPLR C/SLRC RATIO 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Table 20 Master Mode MCLK:LRCLK Ratio Select Table 21 shows the settings for PAIFTX_RATE, PAIFRX_RATE and SAIFRATE for common sample rates and MCLK frequencies.
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Product Preview
SAMPLING RATE (PDATAIPLRC/ PDATAOPLRC) 128fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =000
WM8777
SYSTEM CLOCK FREQUENCY (MHZ)
192fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =001
256fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =010
384fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =011
512fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =100
768fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =101
1152fs
PAIFTX_RATE/ PAIFRX_RATE/ SAIFRATE =110
32kHz 44.1kHz 48kHz 96kHz 192kHz
4.096 5.6448 6.144 12.288 24.576
6.144 8.467 9.216 18.432 36.864
8.192 11.2896 12.288 24.576 Unavailable
12.288 16.9340 18.432 36.864 Unavailable
16.384 22.5792 24.576 Unavailable Unavailable
24.576 33.8688 36.864 Unavailable Unavailable
36.864 Unavailable Unavailable Unavailable Unavailable
Table 21 Master Mode ADC/PDATAIPLRC Frequency Selection PBCLK is also generated by the WM8777. The frequency of PBCLK depends on the mode of operation. In 128/192fs modes (PAIFTX_RATE/PAIFRX_RATE=000 or 001) PBCLK = MCLK/2. In 256/384/512/768/1152fs modes (PAIFTX_RATE/PAIFRX_RATE=010 or 011 or 100 or 101 or 110) PBCLK = MCLK/4. However if DSP mode is selected as the audio interface mode then PBCLK=MCLK. This is to ensure that there are sufficient PBCLKs to clock in all eight channels. Note that DSP mode cannot be used in 128fs mode for word lengths greater than 16-bits or in 192fs mode for word lengths greater than 24 bits.
Figure 15 Digital Audio Data Timing - Master Mode
Test Conditions DVDD = 3.3V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, ADC/DAC in Slave Mode unless otherwise stated. PARAMETER PDATAOPLRC/PDATAIPL RC propagation delay from PBCLK falling edge PDATAOP propagation delay from PBCLK falling edge PDATAIP1/2/3/4 setup time to PBCLK rising edge PDATAIP1/2/3/4 hold time from PBCLK rising edge SYMBOL tDL TEST CONDITIONS MIN 0 TYP MAX 10 UNIT ns
Audio Data Input Timing Information
tDDA
0
10
ns
tDST tDHT
10 10
ns ns
Table 22 Digital Audio Data Timing - Master Mode
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WM8777
MASTER MODE REGISTERS
Product Preview
Control bit PAIFRX_MS selects between primary audio interface Master and Slave Modes. Control bit SMS selects between secondary audio interface master and slave modes. REGISTER ADDRESS (19h) Master Mode Control BIT 7 LABEL
PAIFTX_MS
DEFAULT 0
DESCRIPTION Master/Slave Interface mode select. If ADCCLKSRC is set high then this register control whether the ADC clocks are in master or slave mode/ 0 = Slave Mode - PDATAOPLRC and ADCPBCLK are inputs 1 = Master Mode - PDATAOPLRC and ADCPBCLK are outputs Maser/Slave interface mode select 0 = Slave Mode - PDATAOPLRC, PDATAIPLRC and PBCLK are inputs 1 = Master Mode - PDATAOPLRC, PDATAIPLRC and PBCLK are outputs Note if ADCCLKSRC is set high then this register only controls PDATAIPLRC and PBCLK. Master/Slave interface mode select 0 = Slave Mode - SLRC and SPBCLK are inputs 1 = Master Mode - SLRC and SPBCLK are outputs
8
PAIFRX_MS
0
(3Fh) Secondary Interface Master Mode Control
3
SMS
0
Table 23 Master Mode Registers In Master mode the WM8777 generates PDATAOPLRC, PDATAIPLRC and PBCLK. These clocks are derived from master clock and the ratio of MCLK to PDATAOPLRC and PDATAIPLRC are set by PAIFTX_RATE, PAIFRX_RATE and SAIFRATE. REGISTER ADDRESS (19h) Master Mode Control BIT 2:0 LABEL PAIFTX_RATE [2:0] PAIFRX_RATE [2:0] SAIFRATE [2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK:LRCLK ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Audio interface master clock source when SMS is 1. 00 = MCLK 01 = GPIO (If ADCCLKSRC is set) 10 = PLL clock 11 = PLL clock
6:4 (3Fh) Secondary Interface Master Mode Control
010
2:0
010
(3Fh) Secondary Interface
5:4
SAIFCLKSRC[1:0]
00
Table 24 Master Mode MCLK:LRCLK Regsiters
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Product Preview
WM8777
AUDIO INTERFACE FORMATS
Audio data is applied to the WM8777 via the Primary and Secondary Audio Interface. Five popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP Early mode DSP Late mode
All five formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. Audio Data for each stereo channel is time multiplexed with the interface's Left-Right-Clock (PDATAOPLRC/PDATAIPLRC), indicating whether the left or right channel is present. The PDATAOPLRC/PDATAIPLRC is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and IS modes, the minimum number of PBCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of word length PBCLKs and low for a minimum of word length PBCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met. The Primary Audio interface has Left-Right-Clocks PDATAOPLRC and PDATAIPLRC, and Bit-Clock PBCLK. The Secondary Audio Interface has Left-Right-Clock SLRC, and Bit-Clock SPBCLK. In DSP early or DSP late mode, all 8 DAC channels are time multiplexed onto PDATAIP1. PDATAIPLRC is used as a frame sync signal to identify the MSB of the first word. The minimum number of PBCLKs per PDATAIPLRC period is 8 times the selected word length. Any mark to space ratio is acceptable on PDATAIPLRC provided the rising edge is correctly positioned. The ADC data may also be output in DSP early or late modes, with PDATAOPLRC used as a frame sync to identify the MSB of the first word. The minimum number of PBCLKs per PDATAOPLRC period is 2 times the selected word length. The Secondary Audio Interface also supports DSP modes with SLRC used as a frame sync and data input on SDATAIP, and data output on SDATAOP. The minimum number of SPBCLKs per SLRC period is 2 times the selected word length.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of the input data (PDATAIP/SDATAIP) is sampled by the WM8777 on the first rising edge of PBCLK/SPBCLK following a LRCLK transition. The MSB of the output data (PDATAOP/SDATAOP) changes on the same falling edge of PBCLK as SLRC, and may be sampled on the next rising edge of PBCLK. LRCLKs are high during the left samples and low during the right samples.
Figure 16 Left Justified Mode Timing Diagram
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WM8777
RIGHT JUSTIFIED MODE
Product Preview
In right justified mode, the LSB of the input data (PDATAIP/SDATAIP) is sampled by the WM8777 on the rising edge of PBCLK/SPBCLK preceding a LRCLK transition. The LSB of the output data (PDATAOP/SDATOP) changes on the falling edge of PBCLK preceding a LRCLK transition, and may be sampled on the nect rising edge of PBCLK. LRCLKs are high during the left samples and low during the right samples (Figure 17).
Figure 17 Right Justified Mode Timing Diagram
I S MODE
In I2S mode, the MSB of the input data is sampled by the WM8777 on the second rising edge of PBCLK/SPBCLK following a LRCLK transition. The MSB of the output data changes on the first falling edge of PBCLK following an LRCLK transition, and may be sampled on the next rising edge of PBCLK. LRCKs are low during the left samples and high during the right samples.
2
Figure 18 I2S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the MSB of DAC channel 1 left data is sampled by the WM8777 on the second rising edge on PBCLK following a PDATAIPLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data follow DAC channel 1 left data (Figure 19).
Figure 19 DSP Early Mode Timing Diagram - DAC Data Input
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Product Preview
WM8777
The MSB of the left channel ADC data is output on PDATAOP and changes on the first falling edge of PBCLK following a low to high PDATAOPLRC transition and may be sampled on the rising edge of PBCLK. The right channel ADC data is contiguous with the left channel data (Figure 20).
Figure 20 DSP Early Mode Timing Diagram - ADC Data Output
DSP LATE MODE
In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8777 on the first PBCLK rising edge following a PDATAIPLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data follow DAC channel 1 left data (Figure 21).
Figure 21 DSP Late Mode Timing Diagram - DAC Data Input The MSB of the left channel ADC data is output on PDATAOP and changes on the same falling edge of PBCLK as the low to high PDATAOPLRC transition and may be sampled on the rising edge of PBCLK. The right channel ADC data is contiguous with the left channel data (Figure 22).
Figure 22 DSP Late Mode Timing Diagram - ADC Data Output In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 6 channels. No PBCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4 right. For DSP modes the Secondary Audio Interface exhibits similar timing to the ADC where data is input on SDATAIP, and output on SDATAOP.
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WM8777
DIGITAL AUDIO INTERFACE CONTROL REGISTERS
Product Preview
Interface format for primary and secondary interfaces are selected via the PAIFRX_FMT register bits: REGISTER ADDRESS (18h) Primary Interface Control (RX) BIT 1:0 LABEL PAIFRX_FMT [1:0] DEFAULT 10 DESCRIPTION Interface Format Select 00 = right justified mode 01 = left justified mode 10 = I2S mode 11 = DSP (early or late) mode
(1Bh) Primary Interface Control (TX) (3Eh) Secondary Interface Control Table 25 Format Registers
1:0
PAIFTX_FMT [1:0] SAIF_FMT [1:0]
10
1:0
10
In left justified, right justified or I2S modes, the PAIFRX_LRP register bit controls the polarity of PDATAIPLRC/PDATAOPLRC/SLRC. If this bit is set high, the expected polarity of PDATAIPLRC/PDATAOPLRC/SLRC will be the opposite of that shown in Figure 16, Figure 17 and Figure 18. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the PAIFRX_LRP register bit is used to select between early and late modes. REGISTER ADDRESS (18h) Primary Interface Control (RX) BIT 2 LABEL PAIFRX_LRP DEFAULT 0 DESCRIPTION In LEFT/RIGHT/I2S modes:
PDATAOPLRC/PDATAIPLRC/SLRC
Polarity (normal) 0 = normal LRCLK polarity 1 = inverted LRCLK polarity 2 PAIFTX_LRP 0 In DSP mode: 0 = Early DSP mode 1 = Late DSP mode
(1Bh) Primary Interface Control (TX) (3Eh) Secondary Interface Control
2
SAIF_LRP
0
Table 26 LRCLK Polarity Registers By default, PDATAIPLRC, PDATAOPLRC, SLRC, PDATAIP1/2/3/4 and SDATAIP are sampled on the rising edge of PBCLK/SPBCLK and should ideally change on the falling edge. Data sources that change PDATAIPLRC, PDATAOPLRC, SLRC, PDATAIP1/2/3/4 and SDATAOP on the rising edge of PBCLK/SPBCLK can be supported by setting the PAIFRX_BCP register bit. Setting PAIFRX_BCP to 1 inverts the polarity of PBCLK/SPBCLK to the inverse of that shown in Figure 19, Figure 20, Figure 21 and Figure 22. REGISTER ADDRESS (18h) Primary Interface Control (RX) (1Bh) Primary Interface Control (TX) BIT 3 LABEL PAIFRX_BCP DEFAULT 0 DESCRIPTION PBCLK/SPBCLK Polarity (DSP modes) 0 = normal PBCLK polarity 1 = inverted PBCLK polarity
3
PAIFTX_BCP
0
(3Eh) 3 SAIF_BCP Secondary Interface Control Table 27 PBCLK Polarity Registers
0
The PAIFRX_WL[1:0] bits are used to control the input word length. Note: If 32-bit mode is selected in right justified mode, the WM8777 defaults to 24 bits.
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Product Preview
WM8777
REGISTER ADDRESS (18h) Primary Interface Control (RX) (1Bh) Primary Interface Control (TX) (3Eh) Secondary Interface Control BIT 5:4 LABEL PAIFRX_WL[1:0] DEFAULT 10 DESCRIPTION Input Word Length 00 = 16 bit data 01 = 20 bit data 10 = 24 bit data 11 = 32 bit data
5:4
PAIFTX_WL [1:0]
10
5:4
SAIF_WL [1:0]
10
Table 28 Word Length Registers In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8777 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit IS mode, any width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 PBCLKs and low for a minimum of 24 PBCLKs. If exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode.
POWERDOWN MODES
The WM8777 has powerdown control bits allowing specific parts of the WM8777 to be powered down when not in use. The 6-channel input source selector and input buffer may be powered down using control bit AINPD. When AINPD is set all inputs to the source selector (AIN1L/R to AIN6L/R) are switched to a buffered VMIDADC and the ADC is also powered off. The control bit ADCPO powers off the ADC. The four stereo DACs each have a separate powerdown control bit, DACPD[3:0] allowing individual stereo DACs to be powered down when not in use. The analogue output mixers and PGAs may also be powered down by setting OUTPD1/2/3/4. OUTPD1/2/3/4 also switch the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output. SPDIFTXD and SPDIFRXD will powerdown the S/PDIF transmitter and receiver. Setting all of AINPD, ADCPD, DACPD[3:0], SPDIFTXD, SPDIFRXD and OUTPD[3:0] will powerdown everything except the references VMIDADC, ADCREF and VMIDDAC. These may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the 6-channel input mux and buffer, ADC, DAC and output mixers and PGAs are powered down before setting PDWN. The default is for all powerdown bits to be set except PDWN. REGISTER ADDRESS (1Ah) Powerdown Control BIT 0 LABEL PWDN DEFAULT 0 DESCRIPTION Chip Powerdown Control (works in tandem with the other powerdown registers): 0 = All digital circuits running, outputs are active 1 = All digital circuits in power save mode, outputs muted ADC powerdown: 0 = ADC enabled 1 = ADC disabled DAC powerdowns (0 = DAC enabled, 1 = DAC disabled) DACPD[0] = DAC1 DACPD[1] = DAC2 DACPD[2] = DAC3 DACPD[3] = DAC4 SPDIF_TX powerdown 0 = SPDIF_TX enabled 1 = SPDIF_TX disabled SPDIF_RX powerdown 0 = SPDIF_RX enabled 1 = SPDIF_RX disabled
1
ADCPD
1
5:2
DACPD[3:0]
1111
6
SPDIFTXD
1
7
SPDIFRXD
1
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WM8777
8 OSCPD 1
Product Preview OSC power down 0 = Oscillator enabled 1 = Oscillator disabled Input mux and buffer powerdown 0 = Input mux and buffer enabled 1 = Input mux and buffer powered down Mixer Powerdown select 0 = Powerup 1 = Powerdown
(31h) ADC Mux and Buffer Powerdown Control (32h) Output Mux and Powerdown Control 1
8
AINPD
1
7
OUTPD1
1
8
OUTPD2
1
Mixer Powerdown select 0 = Powerup 1 = Powerdown
(33h) Output Mux and Powerdown Control 2
7
OUTPD3
1
Mixer Powerdown select 0 = Powerup 1 = Powerdown
8
OUTPD4
1
Mixer Powerdown select 0 = Powerup 1 = Powerdown
(37h) PLL Control 4 (2Dh) Output Powerdown
0 0
PLLPD AUXLPD
1 1
0 = Enable PLL 1 = Disable PLL Auxiliary left output powerdown. 0 = enabled 1 = disabled Auxiliary left output powerdown. 0 = enabled 1 = disabled Surround left output powerdown. 0 = enabled 1 = disabled Surround Right output powerdown. 0 = enabled 1 = disabled LFE output powerdown. 0 = enabled 1 = disabled Center output powerdown. 0 = enabled 1 = disabled Front Left output powerdown. 0 = enabled 1 = disabled Front Right output powerdown. 0 = enabled 1 = disabled Headphone output powerdown. 0 = enabled 1 = disabled
1
AUXRPD
1
2
SURLPD
1
3
SURRPD
1
4
LFEPD
1
5
CTRPD
1
6
FRTLPD
1
7
FRTRPD
1
8
HPPD
1
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Product Preview R65 (41h) Interface Source Select 5:4 PAIFSRC [1:0] 01
WM8777
Audio Interface output source 00 = S/PDIF received data 01 = ADC digital output data 10 = Secondary Audio Interface received data 11 = Power-down Primary Audio Interface Transmitter Secondary Audio Interface Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Power-down Secondary Audio Interface Transmitter 11 = Primary Audio Interface received data.
7:6
SAIFSRC [1:0]
00
Table 29 Powerdown Registers
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WM8777
MASTER CLOCK AND PHASE LOCKED LOOP
Product Preview
The WM8777 has an on-chip phase-locked loop (PLL) circuit that can be used to: * * Generate master clocks for the WM8777 audio functions from another external clock. Generate a clock for another part of the system from an existing audio master clock.
Figure 23 PLL and Clock Select Circuit The PLL frequency ratio R = f2/f1 (see Figure 23 ) can be set using K and N (see : N = int R K = int (222 (R-N))
Example: MCLK=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < N < 13. There is a divide by 4 and a selectable divide by 2 after the PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f2 = 8 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 N = int R = 8 k = int ( 222 x (8.192 - 8)) = 805306 = C49BAh
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Product Preview
WM8777
S/PDIF DATA/CLOCK RECOVERY
The WM8777 uses a patented clock and data recovery scheme that allows an extremely low jitter bandwidth on the output recovered clock. This is done by isolating the clock and data recovery systems. The data is recovered and stored in a buffer which modifies the frequency of the recovered clock via a filter. This filter controls the jitter bandwidth using the register value FPLL.
SPDIF in
Data recovery
SPDIF out Buffer Clock out
FPLL
Figure 24 S/PDIF Data and Clock Recovery System
Filter
Clock recovery
The jitter bandwidth affects the rate at which the clock can change to track the incoming data rate, resulting in a slower tracking time as FPLL is increased. Note that this effect is only apparent on slowly changing input frequencies. Input signals that change frequency by a significant amount, i.e. data rate changes, will cause the system to lose lock and to enter a quick tracking mode which will open the filter bandwidth out to the maximum. Table 30 lists the cut-off frequencies for the different values of FPLL. REGISTER ADDRESS (42h) S/PDIF Data/Clock Recovery BIT 5:3 LABEL FPLL[2:0] DEFAULT 111 DESCRIPTION -3dB LPF Cut-Off 000 = Invalid 001 = 28.84Hz 010 = 14.92Hz 011 = 7.46Hz 100 = 3.73Hz 101 = 1.87Hz 110 = 0.97Hz 111 = 0.47Hz
Table 30 PLL Frequency Ratio Control
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WM8777
REGISTER ADDRESS (18h) Primary Interface Control (RX) BIT 6 LABEL MCLKOPEN DEFAULT 0 DESCRIPTION
Product Preview
MCLK pin output enable 0 = MCLK pin is an input 1 = MCLK pin is an output (refer to MCLKOUTSRC below MCLK pin output source 0 = PLL 1 = Crystal clock output. Fractional (K) part of PLL input/output frequency ratio (treat as one 22-digit binary number).
7
MCLKOUTSRC
0
(34h) PLL Control 1 (35h) PLL Control 2 (36h) PLL Control 3
8:0 8:0 3:0 4
PLL_K[8:0] PLL_K[17:9] PLL_K[21:18] CLKOUTSRC
121 (Hex) 17E (Hex) D(Hex) 0
CLKOUT pin source:0 = PLL clock output 1 = Crystal clock output. DAC clock source 0 = MCLK pin 1 = PLL clock ADC clock source 0 = MCLK or ADCMLCK pin 1 = PLL clock S/PDIF TX clock source 0 = MLCK or ADCMCLK pin 1 = PLL clock 0 = Enable PLL 1 = Disable PLL 0 = no post scale 1= divide PLL by 2 after PLL 0 = Integer N only PLL 1 = Integer N and Fractional K PLL 0 = no pre-scale 1 = divide MCLK by 2 prior to PLL Integer (N) divisor part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. ADC clock source 0 = ADCMCLK is from MCLK pin and ADCPBCLK is from PBCLK pin. 1 = ADCMCLK is from GPIO1, and ADCPBCLK is from GPIO2.(Note that when in this mode RXINSEL must not be set to 01 or 10)
6
PLL2DAC
0
7
PLL2ADC
0
8
PLL2TX
1
(37h) PLL Control 4
0 1 2 3 8:4
PLLPD POSTSCALE FRAC_EN PRESCALE PLL_N[4:0]
1 0 0 0 00000
(40h) S/PDIF Receiver Input Selector
8
ADCCLKSRC
0
Table 31 PLL Frequency Ratio Control Note: MCLKOPEN should not be toggled if any part of the WM8777 is actively using MCLK as its clock source.
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Product Preview
WM8777
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown below. XTALC LK (MHz) (F1) 11.91 11.91 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 F2 (MHz) PRE SCALE POST SCALE R N (Hex) K (Hex)
90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
7.5833 8.2539 7.5264 8.192 6.9474 7.5618 6.272 6.8267 9.408 10.24 9.1785 9.9902 9.1229 9.9297 7.5264 8.192 6.9474 7.5618 6.6901 7.2818
7 8 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7
25545C 103FF6 21B089 C49BA 3CA2F4 23F548 116872 34E818 1A1CAC F5C28 B6D22 3F6017 7DDCA 3B8023 21B089 C49BA 3CA2F4 23F548 2C2B30 12089E
Table 32 PLL Frequency Examples
S/PDIF TRANSCEIVER FEATURES
* * * * * * * * IEC-60958 compatible with 32 to 96k frames/s support Support for Rx and Tx of S/PDIF data Clock synthesis PLL with reference clock input and low jitter output Input mux with support for up to 4 S/PDIF inputs Register controlled Channel Status bit configuration Register read-back of recovered Channel Status bits and error flags Detection of non-audio data, sample rate, de-emphasis Programmable GPO for error flags and frame status flags
An IEC-60958 compatible S/PDIF transceiver is integrated into the WM8777. Operation of the S/PDIF function may be synchronous or asynchronous to the rest of the digital audio circuits. The receiver performs data and clock recovery, and sends recovered data either off the chip to an external DSP (via Primary or Secondary Audio Interfaces), or if the data is audio PCM, it can route the stereo recovered data to DAC1. The recovered clock may be routed out of the chip onto a pin for external use, and may be used to clock the internal DAC and ADC circuits as required. The transmitter generates S/PDIF frames where audio data may be sourced from the ADC, S/PDIF Receiver, Primary or Secondary Audio Interfaces.
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WM8777
S/PDIF FORMAT
Product Preview
S/PDIF is a serial, bi-phase-mark encoded data stream. An S/PDIF frame consists of two subframes. Each sub-frame is made up of: * * * * * * * Preamble - a synchronization pattern used to identify the start of a 192-frame block or subframe 4-bit Auxiliary Data (AUX) - ordered LSB to MSB 20-bit Audio Data (24-bit when combined with AUX) - ordered LSB to MSB Validity Bit - a 1 indicates invalid data in that sub-frame User Bit - over 192-frames, this forms a User Data Block, Channel Bit - over 192-frames, this forms a Channel Status Block Parity Bit - used to maintain even parity over the sub-frame(except the preamble)
An S/PDIF Block consists of 192 frames. Channel and User blocks are incorporated within the 192frame S/PDIF Block. For Consumer mode (as in the WM8777) only the first 40-frames are used to make up the Channel and User blocks. Figure 25 illustrates the S/PDIF format.
Frame 1
.........
Frame 192
Subframe 1
Subframe 2
0
34
Aux
78
Audio Sample Word
27 28
V U C
31
P
Sync preamble
32 bit Word
Figure 25 S/PDIF Format
CLOCK RECOVERY AND GENERATION
The circuit comprises data and clock recovery blocks, and a clock synthesis function in the event of no S/PDIF input. As an integral part of these functions, an accurate, stable, crystal derived master clock must be input to the WM8777. This clock may be generated using the WM8777 crystal oscillator circuit, by connecting a suitable crystal across the XIN XOP pins, or else may be applied as a digital input to the XIN pin. This reference clock input may have any frequency from 10MHz up to 27MHz. When S/PDIF signals are being received, the PLL will recover the audio MCLK at a rate of 256fs or 384fs. In the event of no S/PDIF input, the PLL will continue to synthesise a 128, 256 or 384fs audio clock. If desired the S/PDIF input may be ignored and the PLL instructed to synthesise any desired audio clock rate (depending upon sample rate). The ratio of this audio clock to the reference clock frequency is set by programming the required value over the serial interface. Audio sample rates from 32kHz to 96kHz are supported both by the S/PDIF transceiver and the clock synthesiser. The reference clock input should be low jitter, hence it is recommended that a crystal connected to WM8777 oscillator is used to generate the clock. In this condition very low jitter audio clocks will be generated, and S/PDIF in-coming clocks will likewise be de-jittered. The WM8777 crystal derived clock, or the PLL derived audio clock, may then be supplied to external circuits as low jitter clock references as required.
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WM8777
S/PDIF TRANSMITTER
The S/PDIF transmitter generates the S/PDIF frames, and outputs on the SPDIFOP pin. The audio data for the frame can be taken from one of four sources, selectable using the TXSRC register. The transmitter can be powered down using the SPDIFTXD register bit. REGISTER ADDRESS BIT LABEL TXSRC[1:0] DEFAULT 00 DESCRIPTION S/PDIF Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Secondary Audio Interface received data 11 = Primary Audio Interface Received data. Only used if TXSRC==00. Configures only the Channel Bit in the S/PDIF frame. 0 = Channel data equal to recovered channel data. 1 = Channel data taken from channel status registers. SPDIF_TX powerdown 0 = SPDIF_TX enabled 1 = SPDIF_TX disabled
(41h) 2:1 Interface Source Select
3
TXRXTHRU
0
(1Ah) Powerdown Control
6
SPDIFTXD
1
Table 33 S/PDIF Tx Control The WM8777 also transmits the preamble and VUCP bits (Validity, User Data, Channel Status and Parity bits).
VALIDITY BIT
Set to 0 (to indicate valid data) - unless TXSRC=00 (S/PDIF receiver), where Validity is set by the receiver.
USER DATA
Set to 0 as User Data configuration is not supported in the WM8777 - if TXSRC=00 (S/PDIF receiver) User Data is set by the receiver.
CHANNEL STATUS
The Channel Status bits form a 192-frame block - transmitted at 1 bit per sub-frame. Each sub-frame forms its own 192-frame block. The WM8777 is a consumer mode device and only the first 40 bits of the block are used. All data transmitted from the WM8777 is stereo, so the channel status data is duplicated for both channels. The only exception to this is the channel number bits (23:20) which can be changed to indicate if the channel is left or right in the stereo image. Bits within this block can be configured by setting the Channel Bit Control registers (see Tables 28-32 ). If TXSRC is the S/PDIF receiver, the Channel bits are transmitted with the same values recovered by the receiver - unless TXRXTHRU is set, in which case they are set by the registers. Note that the WM8777 expects to receive channel status data in consumer format. The channel status bits are defined differently for professional mode. The definitions on the following page do not hold for professional mode.
PARITY BIT
This bit maintains even parity for data as a means of basic error detection. It is generated by the transmitter.
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WM8777
REGISTER ADDRESS (39h) S/PDIF Transmitter Channel Bit Control 1 BIT LABEL CHANNEL STATUS BIT 0 DEFAULT
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DESCRIPTION
0
CON/PRO
0
0 = Consumer Mode 1 = Professional Mode (not supported by WM8777) 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM. 0 = Transmitted data has copyright asserted. 1 = Transmitted data has no copyright assertion. 000 = Data from Audio interface has no preemphasis. 001 = Data from Audio interface has preemphasis. 010 = Reserved (Audio interface has preemphasis). 011 = Reserved (Audio interface has preemphasis). All other modes are reserved and should not be used. S/PDIF Channel status bits. 00 = Only valid mode for consumer applications. All other modes are reserved.
1
AUDIO_N
1
0
2
CPY_N
2
0
5:3
PREEMPH [2:0]
5:3
000
7:6
CHSTMODE [1:0]
7:6
00
Table 34 S/PDIF Tx Channel Bit Control 1 REGISTER ADDRESS (3Ah) S/PDIF Transmitter Channel Bit Control 2 BIT LABEL CHANNEL STATUS BIT 15:8 DEFAULT DESCRIPTION
7:0
CATCODE [7:0]
00000000
Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode.
Table 35 S/PDIF Tx Channel Bit Control 2 REGISTER ADDRESS (3Bh) S/PDIF Transmitter Channel Bit Control 3 BIT LABEL CHANNEL STATUS BIT 19:16 23:20 DEFAULT DESCRIPTION
3:0 5:4
SRCNUM [3:0] CHNUM1[1:0]
0000 00
Source Number. No definitions are attached to data. See S/PDIF specification for details. Channel Number for Subframe 1 CHNUM1 00 01 10 11 Channel Status Bits[23:20] 0000 = Do not use channel number 0001 = Send to Left Channel 0010 = Send to Right Channel 0000 = Do not use channel number Channel Status Bits[23:20] 0000 = Do not use channel number 0001 = Send to Left Channel 0010 = Send to Right Channel 0000 = Do not use channel number
7:6
CHNUM2[1:0]
00
Channel Number for Subframe 2 CHNUM2 00 01 10 11
Table 36 S/PDIF Tx Channel Bit Control 3
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Product Preview REGISTER ADDRESS (3Ch) S/PDIF Transmitter Channel Bit Control 4 BIT LABEL CHANNEL STATUS BIT 27:24 DEFAULT
WM8777
DESCRIPTION
3:0
FREQ[3:0]
0001
Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated. Clock Accuracy of Generated clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency.
5:4
CLKACU[1:0]
29:28
11
Table 37 S/PDIF Tx Channel Bit Control 4 REGISTER ADDRESS (3Dh) S/PDIF Transmitter Channel Bit Control 5 BIT LABEL CHANNEL STATUS BIT 32 DEFAULT DESCRIPTION
0
MAXPAIFRX_WL
1
Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000 = Word Length Not Indicated TXPAIFRX_ WL 001 010 100 101 110 MAXPAIFR X_WL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXPAIFR X_WL==0 16 bits 18 bits 19 bits 20 bits 17 bits
3:1
TXPAIFRX_WL [2:0]
35:33
101
All other combinations reserved 7:4 ORGSAMP [3:0] 39:36 0000 Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated
Table 38 S/PDIF Tx Channel Bit Control 5
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WM8777
S/PDIF RECEIVER
INPUT SELECTOR
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The S/PDIF receiver has one dedicated input, SPIN. There are three other pins which can be configured as either S/PDIF inputs or general purpose outputs (GPOs). The four S/PDIF inputs go into a 4:1 mux, allowing one input to go to the S/PDIF receiver for decoding. The S/PDIF receiver can be powered down using the SPDIFRXD register bit. REGISTER ADDRESS (40h) S/PDIF Receiver Input Selector BIT 0 LABEL SPDINMODE DEFAULT 0 DESCRIPTION Selects the input circuit type for the S/PDIF input 0 = Normal CMOS input 1 = Comparator input. Compatible with 200mV AC coupled consumer S/PDIF input signals. S/PDIF Receiver input mux select. Note that the general purpose inputs must be configured using GPIOxOP to be either CMOS or comparator inputs if selected by RXINSEL. 00 = S/PDIF_IN1 01 = S/PDIF_IN2 (GPIO1) 10 = S/PDIF_IN3 (GPIO2) 11 = S/PDIF_IN4 (GPIO3)
5:4
RXINSEL[1:0]
00
Table 39 S/PDIF Rx Input Selection register
AUDIO DATA HANDLING
The S/PDIF receiver recovers the data and VUCP bits from each sub-frame. If the S/PDIF input data is in PCM format the data can be internally routed to the stereo data input of DAC1. The WM8777 can detect when the data is not in PCM format and will automatically mute the DAC. See Non-Audio Detection for more detail. The received data can also be output over the Audio interfaces in any of the data formats supported. This can be done while simultaneously using DAC1 for playback. The received data may also be retransmitted over SPDIFOP.
USER DATA
The WM8777 can output recovered user data received over the GPIO pins. See Table 48 for General Purpose Pin control.
CHANNEL STATUS DATA
The channel status bits are recovered from the incoming data stream and are used to control various functions of the device. The recovered MAXPAIFRX_WL and PAIFRX_WL bits are used to truncate the recovered 24-bit audio word to so that only the appropriate numbers of bits are used by the other interfaces (except the S/PDIF transmitter which always sees the full 24-bit recovered word). Should the recovered DEEMPH Channel-bit be set, and DAC1 is used for playback, the de-emphasis filter is activated for that DAC. It is assumed that the channel status is stereo and hence only channel 1 data is read. The channel status data is stored in 5 read-only registers which can be read back over the serial interface (see Serial Interface Readback). When the channel status data has been recovered and stored in registers, the CSUD (Channel Status UpDate) bit goes high to indicate that the registers are ready for readback. It will go low again when the first sub-frame of data from the next block is received. CSUD can be output to one of the GPIO pins.
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WM8777
The register descriptions for the channel status bits are given below. Note that the descriptions below refer to consumer mode. The WM8777 may give erroneous behaviour if professional format data is input.
REGISTER ADDRESS (4Ch) S/PDIF Receiver Channel Status Register 1 (read-only)
BIT
LABEL
CHANNEL STATUS BIT 0
DESCRIPTION
0
CON/PRO
0 = Consumer Mode 1 = Professional Mode The WM8777 is a consumer mode device. Detection of professional mode may give erroneous behaviour. Recovered S/PDIF Channel status bit 1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. 0 = Recovered S/PDIF data has no preemphasis. 1 = Recovered S/PDIF data has preemphasis. Reserved for additional de-emphasis modes.
1
AUDIO_N
1
2 3
CPY_N PREEMPH
2 3
5:4
Reserved
5:4
Table 40 S/PDIF Rx Channel Status Register 1 REGISTER ADDRESS (4Dh) S/PDIF Receiver Channel Status Register 2 (read-only) BIT LABEL CHANNEL STATUS BIT 15:8 DESCRIPTION
7:0
CATCODE [7:0]
Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode.
Table 41 S/PDIF Rx Channel Status Register 2 REGISTER ADDRESS (4Eh) S/PDIF Receiver Channel Status Register 3 (read-only) BIT LABEL CHANNEL STATUS BIT 19:16 23:20 DESCRIPTION
3:0 7:4
SRCNUM [3:0] CHNUM1[3:0]
Indicates number of S/PDIF source. Channel number for channel 1. 0000 = Take no account of channel number (channel 1 defaults to left DAC) 0001 = channel 1 to left channel 0010 = channel 1 to right channel
Table 42 S/PDIF Rx Channel Status Register 3
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WM8777
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REGISTER ADDRESS (4Fh) S/PDIF Receiver Channel Status Register 4 (read-only)
BIT
LABEL
CHANNEL STATUS BIT 27:24
DESCRIPTION
3:0
FREQ[3:0]
Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated. Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency.
5:4
CLKACU[1:0]
29:28
Table 43 S/PDIF Rx Channel Status Register 4 REGISTER ADDRESS (50h) S/PDIF Receiver Channel Status Register 5 (read-only) BIT LABEL CHANNEL STATUS BIT 32 DESCRIPTION
0
MAXPAIFRX_WL
Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Audio Sample Word Length. 000: Word Length Not Indicated RXPAIFRX_ WL 001 010 100 101 110 MAXPAIFR X_WL==1 20 bits 22 bits 23 bits 24 bits 21 bits MAXPAIFR X_WL==0 16 bits 18 bits 19 bits 20 bits 17 bits
3:1
RXPAIFRX_WL [2:0]
35:33
All other combinations are reserved and may give erroneous operation. Data will be truncated internally when these bits are set. 7:4 ORGSAMP [3:0] 39:36 Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated
Table 44 S/PDIF Rx Channel Status Register 5
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WM8777
ERROR HANDLING
Several kinds of error can be reported when decoding the incoming data. The error bits are written to a read-only register which can be read back by the user over the serial interface. Reading back this register will reset it.
REGISTER ADDRESS (4Bh) S/PDIF Receiver Error Register (read-only)
BIT 0
LABEL UNLOCK
DEFAULT 0
DESCRIPTION PLL Unlock signal. 0 = PLL is locked to incoming S/PDIF stream. 1 = PLL is not locked to the incoming S/PDIF stream. V bit from S/PDIF input stream. 0 = Data word is valid. 1 = Data word is not valid. Even Parity check. 0 = No Parity errors detected. 1 = Parity error detected. Biphase coding of S/PDIF input stream. 0 = Biphase Coding is correct. 1 = Biphase Coding error detected. Received Channel status bit 1 has changed. 0 = Normal running. 1 = Change on AUDIO_N. PCM_N bit has changed 0 = Normal running. 1 = Change on PCM_N. Received Channel status bit 2 has changed. 0 = Normal running. 1 = Change on CPY_N. S/PDIF mode change. 0: Normal running 1: Change in S/PDIF frequency mode detected.
1
VALIDITY
0
2
PARITYERR
0
3
BIP
0
4
AUDIO_N
0
5
PCM_N
0
6
CPY_N
0
7
SPDIF_MODE
0
Table 45 S/PDIF Rx Error Status Register When an error is detected the INT signal is set high. This is a logical OR of the error bits which can be output to a GPIO (GPIO1 by default). Error bits can be masked off by setting the mask register. If an error bit is masked off then that error will not be written to the error register and will not cause a change on INT. UNLOCK, VALIDITY, PARITY and BIP generate an interrupt when they go from low to high. These bits are sticky, i.e. the interrupt will remain until the user reads back the register to clear it. AUDIO_N, PCM_N, CPY_N and SPDIF_MODE will generate an interrupt on any change in status. The user can then determine the status of these bits by reading back the S/PDIF status register.
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WM8777
REGISTER ADDRESS (51h) S/PDIF Status Register (read-only) BIT 0 LABEL AUDIO_N DEFAULT DESCRIPTION
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Received Channel status bit 1 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Detects non-audio data from a 96-bit sync code, as defined in IEC-61937. 0 = Sync code not detected. 1 = Sync code detected - received data is not audio PCM. Recovered S/PDIF Channel status bit 2. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Note this signal is inverted and will cause an interrupt on logic 0. S/PDIF frequency mode. 00: Mode not supported 01: 88-96KHz 10: 44-48KHz 11: 32KHz
1
PCM_N
2
CPY_N
4:3
SPDIF_MODE
Table 46 S/PDIF Rx Status Register Should the incoming S/PDIF sub-frame contain a PARITY error or a BIP error, it is assumed the subframe has become corrupted. These errors would normally be flagged, but if the error bits have been masked, the WM8777 will instead overwrite the recovered frame (i.e. both sub-frames) with either all-zeros or the last data sample (depending on how FILLMODE has been set). When the flags are unmasked and an error is detected, the data is allowed to pass, albeit still corrupted. Similarly, if VALIDITY is detected as 1, it is assumed the data within the S/PDIF frame is invalid. If VALIDITY is masked, then data is overwritten depending on FILLMODE, else VALIDITY is flagged and the (invalid) data is allowed to pass. (Note1: ALWAYSVALID must be set to 0, else the recovered VALIDITY bit will be ignored). (Note 2: For the S/PDIF Receiver to S/PDIF transmitter path, only masked VALIDITY errors will cause data to be overwritten - PARITY and BIP errors have no effect).
REGISTER ADDRESS (49h) S/PDIF Receiver Error Mask
BIT 7:0
LABEL MASK[7:0]
DEFAULT 0000000
DESCRIPTION When a lag is masked, it does not update the Error Register or contribute to the interrupt pulse. 0 = unmask, 1 = mask. MASK[0] = mask control for UNLOCK MASK[1] = mask control for VALIDITY MASK[2] = mask control for PARITYERR MASK[3] = mask control for BIP MASK[4] = mask control for AUDIO_N MASK[5] = mask control for PCM_N MASK[6] = mask control for CPY_N MASK[7] = mask control for SPDIF_MODE Determines what SPDIF_RX should do if the validity bit indicates invalid data: 0 = Data from SPDIF_RX remains static at last valid sample. 1 = Data from SPDIF_RX is output as all zeros. Used to override the recovered validity bit. 0 = Use validity bit. 1 = Ignore validity bit.
(40h) S/PDIF Receiver Input Selector
6
FILLMODE
0
7
ALWAYSVALID
0
Table 47 S/PDIF Rx Error Mask Register
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WM8777
The circuit for dealing with UNLOCK, VALIDITY, PARITY and BIP errors is shown in Figure 26.
Error bit[0/1/2/3] RegisterReadDone
SET CLR
Set Domiant
Serial Interface Readback
Mask bit[0/1/2/3]
INT
Figure 26 S/PDIF Error Handling Circuit for UNLOCK, VALIDITY, PARITY and BIP Errors
NON-AUDIO DETECTION
Non-Audio data is indicated by the AUDIO_N and PCM_N bits. AUDIO_N is recovered from the Channel Status block. PCM_N is set on detection of the 96-bit IEC-61937 non-audio data sync code, embedded in the data section of the S/PDIF frame. When either the AUDIO_N or PCM_N bits are set in the error register, and DAC1 is being used for playback, the DAC will be muted automatically using the softmute feature. As described above, any change on AUDIO_N or PCM_N will cause an interrupt to be generated. If the MASK register bit for AUDIO_N or PCM_N is set, then that signal will not generate an interrupt but will still mute the DAC. If non-audio data is detected and the DAC has been muted, the user must ensure that audio data is being input, then clear the error register. The mute on the DAC will be removed when the WM8777 detects that audio data is being received.
GENERAL PURPOSE INPUT AND OUTPUT (GPIO) PINS
The WM8777 has four pins which can be additionally configured as GPIOs, using the registers shown in Table 48. The GPIO pins can be used to output control and status data decoded by the S/PDIF receiver REGISTER ADDRESS (47h) GPIO Control 1 (48h) GPIO Control 2 BIT 3:0 7:4 3:0 7:4 LABEL GPIO1OP[3:0] GPIO2OP[3:0] GPIO3OP[3:0]
GPOMODEOP
DEFAULT 0000 0001 0010 1010
DESCRIPTION 0000 = INT 0001 = V - Validity 0010 = U - User Data bit 0011 = C - Channel Status Data 0100 = P - Parity bit 0101 = Non-audio (AUDIO_N || PCM_N) 0110 = UNLOCK 0111 = CSUD (Channel Status Registers Updated) 1000 = Zero Flag 1 output 1001 = Zero Flag 2 output 1010 = GPIOx set as S/PDIF input (standard CMOS input buffer). Not valid for GPOMODE. 1011 = GPIOx set as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals). Not valid for GPOMODE. 1100 = Sub Frame clock (1 = sub-frame1, 0 = subframe2) 1101 = Start of Block signal
[3:0]
Table 48 GPIO Control Registers
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WM8777
DAC CONTROL REGISTERS
DAC INPUT CONTROL
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The primary audio interface has a separate input pin for each stereo DAC. Any input pin can be routed to any DAC using the DACxSEL register bits. REGISTER ADDRESS (38h) DAC Digital Input Selector BIT 1:0 3:2 5:4 7:6 LABEL DAC1SEL [1:0] DAC2SEL [1:0] DAC3SEL [1:0] DAC4SEL [1:0] DEFAULT 00 01 10 11 DESCRIPTION DAC digital input select. 00 = DAC takes data from PDATAIP1 01 = DAC takes data from PDATAIP2 10 = DAC takes data from PDATAIP3 11 = DAC takes data from PDATAIP4
Table 49 DAC Input Select Register
MUTE MODES
The WM8777 has individual mutes for each of the four DAC channels. Setting MUTE for a channel will apply a `soft' mute to the input of the digital filters of the channel muted. DMUTE[0] mutes DAC channel 1, DMUTE[1] mutes DAC channel 2, DMUTE[2] mutes DAC channel 3 and DMUTE[3] mutes DAC channel 4. Setting the MUTEALL register bit will apply a 'soft' mute to the input of all the DAC digital filters REGISTER ADDRESS (16h) Mute Control BIT 3:0 LABEL DMUTE[3:0] DEFAULT 0000 DESCRIPTION DAC channel soft mute enables: DMUTE[0] = 1, enable softmute on DAC1. DMUTE[1] = 1, enable softmute on DAC2. DMUTE[2] = 1, enable softmute on DAC3. DMUTE[3] = 1, enable softmute on DAC4. DAC channel master soft mute. Mutes all DAC channels: 0 = disable softmute on all DACs. 1 = enable softmute on all DACs.
4
MUTEALL
0
Table 50 Mute Registers
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1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005
WM8777
0.006
Figure 27 Application and Release of Soft Mute Figure 27 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024 or more input samples the DAC will be muted if IZD is set. When MUTE is de-asserted, the output will restart immediately from the current input sample. Note that all other means of muting the DAC channels: setting the PL[3:0] bits to 0, setting the PDWN bit or setting attenuation to 0 will cause much more abrupt muting of the output. The Record outputs may be enabled by setting RECEN, where RECEN enables the REC1L and REC1R outputs. REGISTER ADDRESS (16h) Mute Control BIT 6:5 LABEL RECLEN DEFAULT 00 DESCRIPTION RECL Output Enable 00 = REC output muted 01 = REC output ADCL 10 = REC output DAC1L RECR Output Enable 00 = REC output muted 01 = REC output ADCR 10 = REC output DAC1R
8:7
RECREN
00
Table 51 REC Enable Registers
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WM8777
ZERO FLAG OUTPUT
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The WM8777 has a zero detect circuit for each DAC channel which detects when 1024 consecutive zero samples have been input. Two zero flag outputs (ZFLAG1 and ZFLAG2) may be output through the GPIO pins which may then be used to control external muting circuits. A `1' on ZFLAG1 or ZFLAG2 indicates a zero detect. The zero detect may also be used to automatically enable the DAC mute by setting IZD. The zero flag output may be disabled by setting DZFM to 0000. The zero flag signal for a DAC channel will only be a `1' if that channel is disabled as an input to the output summing stage.
REGISTER ADDRESS (17h) DAC Control
BIT 7:4
LABEL DZFM[3:0]
DEFAULT 0000
DESCRIPTION Selects the ouput for ZFLG1 and ZFLG2 pins (see Table 53). 1 = indicates 1024 consecutive zero input samples on the channels selected 0 = indicates at least one of selected channels has non zero sample in last 1024 inputs
Table 52 DZFM Register
DZFM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
ZFLAG1 Zero flag disabled All channels zero Left channels zero Channel 1 zero Channel 1 zero Channel 1 zero Channel 1 zero Channel 2 zero Channel 2 zero Channel 3 zero Channels 1-3 zero Channel 1 zero Channel 1 left zero Channel 2 left zero Channel 3 left zero Channel 4 left zero
ZFLAG2 Zero flag disabled All channels zero Right channels zero Channels 2-4 zero Channel 2 zero Channel 3 zero Channel 4 zero Channel 3 zero Channel 4 zero Channel 4 zero Channel 4 zero Channels 2 and 3 zero Channel 1 right zero Channel 2 right zero Channel 3 right zero Channel 4 right zero
Table 53 Zero Flag Output Select
INFINITE ZERO DETECT
Setting the IZD register bit will enable the internal infinite zero detect function: REGISTER ADDRESS (15h) DAC Attenuation Control BIT 2 LABEL IZD DEFAULT 0 DESCRIPTION Infinite zero detection circuit control and automute control 0 = Infinite zero detect automute disabled 1 = Infinite zero detect automute enabled
Table 54 IZD Register With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that stereo channels outputs to be muted. Mute will be removed as soon as any channel receives a nonzero input.
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WM8777
DE-EMPHASIS MODE
A digital De-emphasis filter may be applied to each DAC channel. The De-emphasis filter for each stereo channel is enabled under the control of DEEMP[3:0]. DEEMP[0] enables the de-emphasis filter for channel 1, DEEMP[1] enables the de-emphasis filter for channel 2, DEEMP[2] enables the de-emphasis filter for channel 3 and DEEMP[3] enables the de-emphasis filter for channel 4. REGISTER ADDRESS (17h) DAC Control BIT 3:0 LABEL DEEMP[3:0] DEFAULT 0000 DESCRIPTION De-emphasis mode select: DEEMPH[0] = 1, enable Deemphasis on DAC1. DEEMPH[1] = 1, enable Deemphasis on DAC2. DEEMPH[2] = 1, enable Deemphasis on DAC3. DEEMPH[3] = 1, enable Deemphasis on DAC4.
Table 55 De-emphasis Register Refer to Figure 37, Figure 38, Figure 39, Figure 40, Figure 41 and Figure 42 for details of the DeEmphasis modes at different sample rates.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS (15h) DAC Attenuation Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 56 DAC Attenuation Register (PL) DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
DAC OVERSAMPLING RATE SELECT
Control bit DACOSR allow the user to select the DAC internal signal processing oversampling rate. Operation is described in Table 18 and Table 19. REGISTER ADDRESS (19h) DAC Oversampling Rate Select BIT 3 LABEL DACOSR DEFAULT 0 DESCRIPTION DAC oversampling rate select 0: 128x oversampling 1: 64x oversampling
Table 57 DAC Oversampling Rate
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WM8777
ATTENUATOR CONTROL MODE
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Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. When the ATC register bit is unset the right channel gain is applied form the new audio input sample. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations
(15h) DAC Attenuation Control
1
DACATC
0
Table 58 DAC Attenuation Register (DACATC)
ANALOGUE VOLUME CONTROL
The DAC volume may be adjusted independently in both the analogue and digital domain using separate volume control registers. REGISTER ADDRESS (00h) Analogue Attenuation FRONTL BIT 6:0 7 LABEL FRONTLA [6:0]
FRONTLZCEN
DEFAULT 1101011 (0dB) 0
DESCRIPTION Analogue Attenuation control for FRONTL in 1dB steps. See Table 60. FRONTL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store FRONTL in intermediate latch (no change to output) 1 = Store FRONTL and update attenuation on all channels. Analogue Attenuation control for FRONTR in 1dB steps. See Table 60. FRONTR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store FRONTR in intermediate latch (no change to output) 1 = Store FRONTR and update attenuation on all channels. Analogue Attenuation control for CNTR in 1dB steps. See Table 60. CNTR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store CNTR in intermediate latch (no change to output) 1 = Store CNTR and update attenuation on all channels. Analogue Attenuation control for LFE in 1dB steps. See Table 60. LFE zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store LFE in intermediate latch (no change to output) 1 = Store LFE and update attenuation on all channels.
8
UPDATE
Not latched
(01h) Analogue Attenuation FRONTR
6:0 7
FRONTRA [6:0]
FRONTRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(02h) Analogue Attenuation CNTR
6:0 7
CNTRA [6:0] CNTRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(03h) Analogue Attenuation LFE
6:0 7
LFEA [6:0] LFEZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
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Product Preview REGISTER ADDRESS (04h) Analogue Attenuation SURL BIT 6:0 7 LABEL SURLA [6:0] SURLZCEN DEFAULT 1101011 (0dB) 0 DESCRIPTION
WM8777
Analogue Attenuation control for SURL in 1dB steps. See Table 60. SURL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store SURL in intermediate latch (no change to output) 1 = Store SURL and update attenuation on all channels. Analogue Attenuation control for SUR Right in 1dB steps. SURR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store SURR in intermediate latch (no change to output) 1 = Store SURR and update attenuation on all channels. Analogue Attenuation control for AUXL in 1dB steps. See Table 60. AUXL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store AUXL in intermediate latch (no change to output) 1 = Store AUXL and update attenuation on all channels. Analogue Attenuation control for AUXR in 1dB steps. See Table 60. AUXR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store AUXR in intermediate latch (no change to output) 1 = Store AUXR and update attenuation on all channels. Analogue Attenuation control for HPHONEL in 1dB steps. See Table 60. HPHONEL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store HPHONEL in intermediate latch (no change to output) 1 = Store HPHONEL and update attenuation on all channels. Analogue Attenuation control for HPHONER in 1dB steps. See Table 60. HPHONER zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store HPHONER in intermediate latch (no change to output) 1 = Store HPHONER and update attenuation on all channels.
8
UPDATE
Not latched
(05h) Analogue Attenuation SURR
6:0 7
SURRA [6:0] SURRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(06h) Analogue Attenuation AUXL
6:0 7
AUXLA[6:0] AUXLZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(07h) Analogue Attenuation AUXR
6:0 7
AUXRA[6:0] AUXRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(08h) Analogue Attenuation HPHONEL
6:0 7
HPLA[6:0] HPLZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
(09h) Analogue Attenuation HPHONER
6:0 7
HPRA[6:0] HPRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
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REGISTER ADDRESS (0Ah) Analogue Attenuation Master (all channels) BIT 6:0 7 LABEL MASTA[6:0] MZCEN DEFAULT 1101011 (0dB) 0 DESCRIPTION
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Analogue Attenuation control for all DAC gains in 1dB steps. See Table 60. Master zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store gains in intermediate latch (no change to output) 1 = Store gains and update attenuation on all channels.
8
UPDATE
Not latched
Table 59 Analogue Attenuation Registers Each analogue output channel volume can be controlled digitally in an analogue volume stage after the DAC. Attenuation is 0dB by default but can be set between +20dB and -100dB in 1dB steps using the 7 Attenuation control words. All attenuation registers are double latched allowing new values to be pre-latched to several channels before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all pre-latched values to be immediately applied to the DAC channels. A master attenuation register is also included, allowing all volume levels to be set to the same value in a single write. Note: The UPDATE bit is not latched. If UPDATE=0, the Attenuation value will be written to the prelatch but not applied to the relevant ouptut. If UPDATE=1, all pre-latched values will be applied from the next input sample. Writing to MASTA[6:0] overwrites any values previously sent to FRONTL[6:0], CNTR[6:0], SURL[6:0], AUXL[6:0], FRONTR[6:0], LFE[6:0], SURR[6:0], AUXR[6:0]. Register bits FRONTL and FRONTR control the left and right channel attenuation of the Front channels. Register bits CNTR and LFE control the left and right channel attenuation of CNTR and LFE respectively. Register bits SURL and SURR control the left and right channel attenuation of surround channels. Register bits AUXL and AUXR control the left and right channel attenuation of the auxiliary channel. Register bits MASTA can be used to control attenuation of all channels. Table 60 shows how the attenuation levels are selected from the 7-bit words. L/RAx[6:0] 00(hex) : 06(hex) 07(hex) : 6B(hex) 7D(hex) 7E(hex) 7F(hex) ATTENUATION LEVEL -dB (mute) : -dB (mute) -100dB : 0dB (default) +18dB +19dB +20dB
Table 60 Analogue Volume Control Attenuation Levels In addition a zero cross detect circuit is provided for each analogue output volume under the control of bit 7 (xZCEN) in each Analogue attenuation register. When ZCEN is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises audible clicks and `zipper' noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks ( ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOCDAC. REGISTER ADDRESS (15h) Timeout Clock Disable BIT 4 LABEL TOCDAC DEFAULT 0 DESCRIPTION DAC Analogue Zero cross detect timeout disable 0 = Timeout enabled 1 = Timeout disabled
Table 61 Timeout Clock Disable Register
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WM8777
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS (0Bh) Digital Attenuation DACL1
BIT 7:0 8
LABEL LDA1[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation control for DAC1 Left Channel (LSUMOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA1 in intermediate latch (no change to output) 1 = Store LDA1 and update attenuation on all channels Digital Attenuation control for DAC1 Right Channel (RSUMOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA1 in intermediate latch (no change to output) 1 = Store RDA1 and update attenuation on all channels. Digital Attenuation control for DAC2 Left Channel (CNTSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA2 in intermediate latch (no change to output) 1 = Store LDA2 and update attenuation on all channels. Digital Attenuation control for DAC2 Right Channel (LFESOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA2 in intermediate latch (no change to output) 1 = Store RDA2 and update attenuation on all channels. Digital Attenuation control for DAC3 Left Channel (LSURSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA3 in intermediate latch (no change to output) 1 = Store LDA3 and update attenuation on all channels. Digital Attenuation control for DAC3 Right Channel (RSURSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Store RDA3 and update attenuation on all channels. Digital Attenuation control for DAC4 Left Channel (LAUXSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA4 in intermediate latch (no change to output) 1 = Store LDA4 and update attenuation on all channels. Digital Attenuation control for DAC4 Right Channel (RAUXSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA4 in intermediate latch (no change to output) 1 = Store RDA4 and update attenuation on all channels. Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Store gain and update attenuation on all channels.
(0Ch) Digital Attenuation DACR1
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
(0Dh) Digital Attenuation DACL2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
(0Eh) Digital Attenuation DACR2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
(0Fh) Digital Attenuation DACL3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
(10h) Digital Attenuation DACR3
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
(11h) Digital Attenuation DACL4
7:0 8
LDA4[7:0] UPDATE
11111111 (0dB) Not latched
(12h) Digital Attenuation DACR4
7:0 8
RDA4[7:0] UPDATE
11111111 (0dB) Not latched
(13h) Digital Attenuation Master (all channels)
7:0 8
MASTDA[7:0] UPDATE
11111111 (0dB) Not latched
Table 62 Digital Attenuation Registers
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L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex)
ATTENUATION LEVEL - dB (mute) -127.5dB : : : -0.5dB 0dB
Table 63 Digital Volume Control Attenuation Levels The Digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN.
REGISTER ADDRESS (15h) DAC Attenuation Control
BIT 0
LABEL DZCEN
DEFAULT 0
DESCRIPTION DAC Digital Volume Zero Cross Enable: 0 = Zero Cross detect disabled 1 = Zero Cross detect enabled
Table 64 Digital Zero Cross Register
DAC OUTPUT PHASE
The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS (14h) DAC Output Phase BIT 7:0 LABEL PHASE [7:0] DEFAULT 00000000 DESCRIPTION Controls phase of DAC outputs PHASE[0] = 1 inverts phase of DAC1L output PHASE[1] = 1 inverts phase of DAC1R output PHASE[2] = 1 inverts phase of DAC2L output PHASE[3] = 1 inverts phase of DAC2R output PHASE[4] = 1 inverts phase of DAC3L output PHASE[5] = 1 inverts phase of DAC3R output PHASE[6] = 1 inverts phase of DAC4L output PHASE[7] = 1 inverts phase of DAC4R output
Table 65 DAC Output Phase Register
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WM8777
OUTPUT SELECT AND ENABLE CONTROL
Register bits MX1[2:0] to MX4[2:0] control the output select. The output select block consists of a summing stage and an input select switch for each input allowing each signal to be output individually or summed with other signals and output on each analogue output. The default for all outputs is DAC playback only. VOUT1/2/3 may be selected to output DAC playback, AUX, analogue bypass or a sum of these using the output select controls MX1/2/3[2:0]. VOUT4 may be selected to output DAC playback, analogue bypass or a sum of these signals using MX4[1:0]. It is recommended that bypass is not selected for output on more than two stereo channels simultaneously to avoid overloading the input buffer, resulting in a decrease in performance. The output mixers and PGAs can be powered down under control of OUTPD1/2/3/4. Each stereo channel may be powered down separately. Setting OUTPD1/2/3/4 will power off the mixer and PGA and switch the analogue outputs VOUTL/R to VMIDDAC to maintain a dc level on the output. REGISTER ADDRESS (32h) Output Mux and Powerdown Control 1 (33h) Output Mux and Powerdown Control 2 BIT LABEL DEFAULT 001 (DAC playback) 001 (DAC playback) 001 (DAC playback) 01 (DAC playback) DESCRIPTION VOUT1 Output select (see Figure 28)
2:0 5:3 2:0 4:3
MX1[2:0] MX2[2:0] MX3[2:0] MX4[1:0]
VOUT2 Output select (see Figure 28) VOUT3 Output select (see Figure 28)
VOUT4 Output select (see Figure 29)
Table 66 Output Mux Register
Figure 28 MX1/2/3[2:0] Output Select
Figure 29 MX4[1:0] Output Select
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ADC CONTROL REGISTERS
ADC GAIN CONTROL
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The ADC has an analogue input PGA and digital gain control for each stereo channel. Both the analogue and digital gains are adjusted by the same register, LAG for the left and RAG for the right. The analogue PGA has a range of +24dB to -21dB in 0.5dB steps. The digital gain control allows further attenuation (after the ADC) from -21.5dB to -103dB in 0.5dB steps. Table 68 shows how the register maps the analogue and digital gains. REGISTER ADDRESS (2Eh) Attenuation ADC Left BIT 7:0 LABEL LAG[7:0] DEFAULT 11001111 (0dB) 0 DESCRIPTION Attenuation control for left channel ADC gain in 0.5dB steps. See Table 68 Zero Cross enable for left channel ADC 0 = Disable Zero Cross 1 = Enable Zero Cross Attenuation control for right channel ADC gain in 0.5dB steps. See Table 68 Zero Cross enable for right channel ADC 0 = Disable Zero Cross 1 = Enable Zero Cross Left Channel mute control 0 = Channel not muted 1 = Channel muted Left Channel mute control 0 = Channel not muted 1 = Channel muted Attenuator Control 0 = ADC use attenuations as programmed. 1 = Right channel ADC use corresponding left ADC attenuations Time out clock enable/disable 0 = Time out clock enabled. 1 = Time out clock disabled.
8
ZCLEN
(2Fh) Attenuation ADC Right
7:0
RAG[7:0]
11001111 (0dB) 0
8
ZCREN
(30h) Attenuation Control
0
MUTEL
0
1
MUTER
0
2
ADCATC
0
3
TOADC
0
Table 67 ADC Attenuation and Mute Registers LAG/RAG[7:0] ATTENUATION LEVEL (AT OUTPUT) - dB (mute) -103dB : -21.5dB -21dB : 0dB : +23.5dB +24dB ANALOGUE PGA DIGITAL ATTENUATION Digital mute -82dB : -0.5dB 0dB : 0dB : 0dB 0dB
00(hex) 01(hex) : A4(hex) A5(hex) : CF(hex) : FE(hex) FF(hex)
-21dB -21dB : -21dB -21dB : 0dB : +23.5dB +24dB
Table 68 Analogue and Digital Gain Mapping for ADC In addition a zero cross detect circuit is provided for the output PGA volume under the control of bit 7 (ZCEN) in the each attenuation register. When ZCEN is set the attenuation values are only updated when the input signal to the gain stage is close to the analogue ground level. This minimises audible clicks and `zipper' noise as the gain values change. A timeout clock is also provided which will generate an update after a minimum of 131072 master clocks (= ~10.5ms with a master clock of 12.288MHz). The timeout clock may be disabled by setting TOADC.
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WM8777
Each ADC channel also has an individual mute control bit, which mutes the input to the ADC. The ADCATC control bit allows the user to write the same attenuation value (LAG) to both left and right volume control registers, saving on software writes. When setting the ADCATC function it is up to the user to write a new gain value to take effect on both channels. When unsetting the ADCATC function it is up to the user to write a new gain to both the left and right channel gains. The ATC function has no effect when the ALC is enabled. The ADC volume and mute also applies to the bypass signal path.
ADC OVERSAMPLING RATE SELECT
The signal processing for the WM8777 typically operates at an oversampling rate of 128fs for the ADC (ADCOSR=0). The exception to this is for operation with a 128/192fs system clock, where the oversampling rate is 64fs (ADCOSR=1). For the ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate from 128fs to 64fs. For the ADC operation at 192KHz in 128fs or 192fs mode it is recommended that the user set the ADCOSR bit. This changes the ADC signal processing oversample rate from 64fs to 32fs. The ADC digital filters contain a digital highpass filter. This defaults to enabled and can be disabled using software control bit ADCHPD. If the DAC and ADC are using the same MCLK source, and they are in compatible fs modes the ADC and DAC will try to lock their respective clock generators together. This reduces the digital noise on chip and helps the performance of the device. By default this is enabled, but can be disabled by setting SYNC to 1. REGISTER ADDRESS (1Bh) ADC Interface Control BIT 6 LABEL ADCHPD DEFAULT 0 DESCRIPTION ADC Highpass Filter Disable: 0 = Highpass Filter enabled 1 = Highpass Filter disabled ADC oversample rate select 0 = 128x oversampling 1 = 64x oversampling Sync ADC and DAC together. 0 = Enable SYNC function 1 = Disable Sync function
7
ADCOSR
0
8 Table 69 ADC Functions Register
SYNC
0
ADC INPUT MUX
REGISTER ADDRESS (31h) ADC Mux and Powerdown Control BIT 5:0 LABEL AIN[5:0] DEFAULT 00000 DESCRIPTION
ADC input mixer control bits (see Table 71)
Table 70 ADC Input Mux Register Register bits AIN[5:0] control the left and right channel inputs into the stereo ADC. The default is AIN1. However if the analogue input buffer is powered down, by setting AINPD, then all 12-channel mux inputs are switched to buffered VMIDADC. AIN[5:0] 00000 00001 00010 00011 00100 00101 ...... 11111 ADC INPUT MUTE AIN1 AIN2 AIN1 + AIN2 AIN3 AIN3 + AIN1 ....... AIN6 + AIN5 + AIN4 +AIN3 + AIN2 + AIN1
Table 71 ADC Input Mux Control
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LIMITER / AUTOMATIC LEVEL CONTROL (ALC)
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The WM8777 has an automatic PGA gain control circuit, which can function as a peak limiter or as an automatic level control (ALC). In peak limiter mode, a digital peak detector detects when the input signal goes above a predefined level and will ramp the PGA gain down to prevent the signal becoming too large for the input range of the ADC. When the signal returns to a level below the threshold, the PGA gain is slowly returned to its starting level. The peak limiter cannot increase the PGA gain above its static level.
input signal
PGA gain
signal after PGA
Limiter threshold
attack time
Figure 30 Limiter Operation
decay time
In ALC mode, the circuit aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
input signal
PGA gain
signal after ALC
ALC target level
hold time
Figure 31 ALC Operation
decay time
attack time
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WM8777
The gain control circuit is enabled by setting the LCEN control bit. The user can select between Limiter mode and three different ALC modes using the LCSEL control bits. REGISTER ADDRESS (1Eh) ALC Control 2 (1Dh) ALC Control 1 BIT 8 LABEL LCEN DEFAULT 0 DESCRIPTION Enable the PGA gain control circuit. 0 = PGA gain control disabled 1 = PGA gain control enabled ALC/Limiter function select 00 = Limiter 01 = ALC Right channel only 10 = ALC Left channel only 11 = ALC Stereo
8:7
LCSEL[1:0]
00
Table 72 ALC Control Registers The limiter function only operates in stereo, which means that the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When enabled, the threshold for the limiter or target level for the ALC is programmed using the LCT control bits. This allows the threshold/target level to be programmed between -1dB and -16dB in 1dB steps. Note that for the ALC, target levels of -1dB and -2dB give a threshold of -3dB. This is because the ALC can give erroneous operation if the target level is set too high. REGISTER ADDRESS (1Dh) ALC Control 1 BIT 3:0 LABEL LCT[3:0] DEFAULT 1011 (-6dB) DESCRIPTION Limiter Threshold/ALC target level in 1dB steps. 0000 = -16dB FS 0001 = -15dB FS ... 1101 = -3dB FS 1110 = -2dB FS 1111 = -1dB FS
Table 73 Limiter Threshold Register
ATTACK AND DECAY TIMES
The limiter and ALC have different attack and decay times which determine their operation. However, the attack and decay times are defined slightly differently for the limiter and for the ALC. DCY and ATK control the decay and attack times, respectively. Decay time (Gain Ramp-Up). When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from -21dB up to +20 dB). When in limiter mode, it is defined as the time it takes for the gain to ramp up by 6dB. The decay time can be programmed in power-of-two (2n) steps. For the ALC this gives times from 33.6ms, 67.2ms, 134.4ms etc. to 34.41s. For the limiter this gives times from 1.2ms, 2.4ms etc., up to 1.2288s. However, the decay time for the limiter can also be made dependant on the input frequency by setting the FDECAY control bit. For a 1kHz input signal this gives decay times of 24ms, 48ms etc., up to 24.576s. Attack time (Gain Ramp-Down) When in ALC mode, this is defined as the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from +20dB down to -21dB gain). When in limiter mode, it is defined as the time it takes for the gain to ramp down by 6dB. The attack time can be programmed in power-of-two (2n) steps, from 8.4ms, 16.8ms, 33.6ms etc. to 8.6s for the ALC and from 250us, 500us, etc. up to 256ms. The time it takes for the recording level to return to its target value or static gain value therefore depends on both the attack/decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack/decay time.
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REGISTER ADDRESS (1Fh) ALC Control 3
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BIT 3:0
LABEL ATK[3:0]
DEFAULT 0010
DESCRIPTION LC attack (gain ramp-down) time ALC mode 0000 = 8.4ms 0001 = 16.8ms 0010 = 33.6ms... (time doubles with every step) 1010 or higher = 8.6s Limiter Mode 0000 = 250us 0001 = 500us... 0010 = 1ms (time doubles with every step) 1010 or higher = 256ms Limiter mode 0000 = 1.2ms 0001 = 2.4ms 0010 = 4.8ms ....(time doubles for every step) 1010 or higher = 1.2288s
7:4
DCY[3:0]
0011
LC decay (gain ramp-up) time ALC mode 0000 = 33.5ms 0001 = 67.2ms 0010 = 134.4ms ....(time doubles for every step) 1010 or higher = 34.41ms
8
FDECAY
0
Frequency dependant decay (limiter only) 0 = Frequency dependent delay disabled 1 = Frequency dependent delay enabled DCY 0000 0001 0010 ...... 1010 or higher 20kHz input (or disabled) 1.2ms 2.4ms 4.8ms ...... 1.2288ms 1kHz input 24ms 28ms 96ms ...... 24.576s
Table 74 ALC Attack and Decay Registers
TRANSIENT WINDOW (LIMITER ONLY)
To prevent the limiter responding to short duration high amplitude signals (such as hand-claps in a live performance), the limiter has a programmable transient window preventing it responding to signals above the threshold until their duration exceeds the window period. The Transient window is set in register TRANWIN. REGISTER ADDRESS (21h) Limiter Control BIT 6:4 LABEL TRANWIN [2:0] DEFAULT 010 DESCRIPTION Length of Transient Window 000 = 0us (disabled) 001 = 62.5us 010 = 125us ..... 111 = 4ms
Table 75 Transient Window Register
ZERO CROSS
The PGA has a zero cross detector to prevent gain changes introducing noise to the signal. In ALC mode the register bit ALCZC allows this to be turned on if desired. REGISTER ADDRESS (1Eh) ALC Control 2 BIT 7 LABEL ALCZC DEFAULT 0 (disabled) DESCRIPTION ALC zero cross detection circuit. 0 = Zero cross detection disabled. 1 = Zero cross detection enabled.
Table 76 ALC Zero Cross Register When the limiter is enabled the zero cross detector on the PGA is automatically enabled to ensure that no noise is introduced during gain changes.
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WM8777
MAXIMUM GAIN (ALC ONLY) AND MAXIMUM ATTENUATION
To prevent low level signals being amplified too much by the ALC, the MAXGAIN register sets the upper limit for the gain. This prevents low level noise being over-amplified. The MAXGAIN register has no effect on the limiter operation. The MAXATTEN register has different operation for the limiter and for the ALC. For the limiter it defines the maximum attenuation below the static (user programmed) gain. For the ALC, it defines the lower limit for the gain. REGISTER ADDRESS (1Dh) ALC Control 1 BIT 6:4 LABEL MAXGAIN[2:0] DEFAULT 111 (+24dB) DESCRIPTION Set maximum gain for the PGA (ALC only) 111 = +24dB 110 = +20dB .....(-4dB steps) 010 = +4dB 001 = 0dB 000 = 0dB Maximum attenuation of PGA Limiter (attenuation below static) 0000 = -3dB 0001 = -4dB 0010 = -5dB .... (-1dB steps) 1001 = -12dB ALC (lower PGA gain limit) 1010 or lower = -1dB 1011 = -5dB ..... (-4dB steps) 1110 = -17dB 1111 = -21dB
(21h) Limiter Control
3:0
MAXATTEN [3:0]
0110
Table 77 ALC MAXGAIN and MAXATTEN Registers
HOLD TIME (ALC ONLY)
The ALC also has a hold time, which is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7ms. Alternatively, the hold time can also be set to zero. The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. REGISTER ADDRESS (1Eh) ALC Control 2 BIT 3:0 LABEL HLD[3:0] DEFAULT 0000 DESCRIPTION ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s
Table 78 ALC Hold Time Register
OVERLOAD DETECTOR (ALC ONLY)
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes an overload detector. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. (Note: If ATK = 0000, then the overload detector makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used).
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NOISE GATE (ALC ONLY)
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When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8777 has a noise gate function that prevents noise pumping by comparing the signal level at the AINL1/2/3/4/5 and/or AINR1/2/3/4/5 pins against a noise gate threshold, NGTH. The noise gate cuts in when: * * Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB]
This is equivalent to: Signal level at input pin [dB] < NGTH [dB]
When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it would normally when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS (20h) Noise Gate Control BIT 0 LABEL NGAT DEFAULT 0 DESCRIPTION Noise gate function enable 0 = Noise gate disabled 1 = Noise gate enabled Noise gate threshold (with respect to ADC output level) 000 = -78dBFS 001 = -72dBfs ... 6 dB steps 110 = -42dBFS 111 = -30dBFS
4:2
NGTH[2:0]
000
Table 79 Noise Gate Registers Note: The Noise Gate should be set after the ALC to ensure correct operation.
SOFTWARE REGISTER RESET
Writing to register 1111111 will cause a register reset, resetting all register bits to their default values. Note that the WM8777 is powered down by default so writing to this register will power down the device.
REGISTER ADDRESS (7Fh) Software reset
BIT
LABEL
DEFAULT
DESCRIPTION Writing to this register will apply a reset to the device registers.
8:0
RESET
Table 80 Software Reset Register
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REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8777 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER B15 B14 B13 B12 R0(00h) R1(01h) R2(02h) R3(03h) R4(04h) R5(05h) R6(06h) R7(07h) R8(08h) R9(09h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B11 B10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B9 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LCSEL[1:0] LCEN FDECAY 0 0 0 0 0 0 0 CNTR AIN6 ALCZC 0 DCY[3:0] 0 0 TRANWIN[2:0] FBYP CNTRGAIIN[2:0] FBM NGTH[2:0] RECREN[1:0] 0 0 PAIFRX MS OSCPD SYNC MLCKOUT SRC PAIFTX_MS SPDIFRXD ADCOSR B8 B7 B6 B5 B4 B3 FRONTLA[6:0] FRONTRA[6:0] CNTRA[6:0] LFEA[6:0] SURLA[6:0] SURRA[6:0] AUXLA[6:0] AUXRA[6:0] HPLA[6:0] HPRA[6:0] MASTA[6:0] LDA1[7:0] RDA1[7:0] LDA2[7:0] RDA2[7:0] LDA3[7:0] RDA3[7:0] LDA4[7:0] RDA4[7:0] MASTDA[7:0] PHASE[7:0] PL[3:0] RECLEN[1:0] DZFM[3:0] MCLKOPEN PAIFRX_WL[1:0] PAIFRX BCP
DACOSR
B2
B1
B0
DEFAULT X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X01101011 X11111111 X11111111 X11111111 X11111111 X11111111 X11111111 X11111111 X11111111 X11111111 000000000
UPDATE FRONTLZCEN UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE UPDATE 0
FRONTRZCEN CNTRZCEN LFEZCEN SURLZCEN SURLZCEN AUXLZCEN AUXRZCEN HPLZCEN HPRZCEN
R10(0Ah) 0 R11(0Bh) 0 R12(0Ch) 0 R13(0Dh) 0 R14(0Eh) 0 R15(0Fh) R16(10h) R17(11h) R18(12h) R19(13h) R20(14h) R21(15h) R22(16h) R23(17h) R24(18h) R25(19h) 0 0 0 0 0 0 0 0 0 0 0
MZCEN
TOCDAC
MUTEALL
0
IZD
DACATC
DZCEN
100100000 000000000 000000000 000100010 000100010 111111110 000100010 000000000
DMUTE[3:0] DEEMP[3:0] PAIFRX LRP PAIFRX_FMT[1:0]
PAIFRX_RATE[2:0] SPDIFTXD ADCHPD
PAIFTX_RATE[2:0] ADCPD PAIFTX LRP PWDN
R26(1Ah) 0 R27(1Bh) 0 R28(1Ch) 0 R29(1Dh) 0 R30(1Eh) 0 R31(1Fh) R32(20h) R33(21h) R34(22h) R35(23h) 0 0 0 0 0
DACPD[3:0] PAIFTX_WL [1:0] Reserved PAIFTX BCP
PAIFTX_FMT[1:0]
MAXGAIN[2:0] 0 0
LCT[3:0] HLD[3:0] ATK[3:0] 0 MAXATTEN[3:0] FBASS[1:0] FLFE FTRBL[1:0] FLFEGAIN[2:0] NGAT
001111011 000000000 100110010 000000000 010100110 000000000 000000000
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WM8777
REGISTER B15 B14 B13 B12 R36(24h) R37(25h) R38(26h) R39(27h) R40(28h) R41(29h) R42(2Ah) R43(2Bh) R44(2Ch) R45(2Dh) R46(2Eh) R47(2Fh) R48(30h) R49(31h) R50(32h) R51(33h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 B11 B10 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B9 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 B8 0 0 0 0 UPDATE UPDATE UPDATE UPDATE UPDATEL HPPD ZCLEN ZCREN 0 AINPD OUTPD2 OUTPD4 0 0 OUTPD1 OUTPD3 0 0 0 0 0 MX2[2:0] MX4[1:0] 0 B7 0 0 0 0 0 0 0 0 UPDATER FTRPD B6 0 HPSEL 0 0 0 0 0 0 UPDATEC FTLPD B5 0 CBYP 0 0 0 0 0 0 FTLP[1:0] CTRPD LFEPD B4 0 CBM 0
0
Product Preview
B3 REAR CBASS[1:0] CLFE
SURRBYP SURLBYP
B2
B1 REARGAIN[2:0]
B0
DEFAULT 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 000000000 111111111 011001111 011001111
CTRBL[1:0] CLFEGAIN[2:0]
AUXRBYP AUXLBYP
0 0 0 0 FTRP[1:0]
FBASS[3:0] FTREB[3:0] CBASS[3:0] CTREB[3:0] CNTP[1:0] AUXLPD
SURRPD SURLPD AUXRPD
LAG[7:0] RAG[7:0] 0 TOADC ADC ATC MUTER MUTEL
000000000 100000000
AIN[5:0] MX1[2:0] MX3[2:0]
110001001 110001001
R52(34h)
0
1
1
0
1
0
0
PLL_K[8:0]
100100001
R53(35h) R54(36h) R55(37h) R56(38h) R57(39h) R58(3Ah) R59(3Bh) R60(3Ch) R61(3Dh) R62(3Eh) R63(3Fh)
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1 1
0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 ADCCL KSRC 0 0 0 0 CHNUM2[1:0] 0 0 PLL2TX PLL2 ADC PLL2 DAC PLL_N[4:0] DAC4SEL[1:0] CHSTMODE[2:0] 0
PLL_K[17:9] CLKOUTS RC PLL_K[21:18] PRESCALE FRAC_E POSTSCA LE N DAC3SEL[1:0] PREEMPH[2:0] CATCODE[7:0] CHNUM1[1:0] CLKACU[1:0] SRCNUM[3:0] FREQ[3:0] TXPAIFRX_WL[1:0] SAIF_WL [1:0] SAIFCLKSRC[1:0] SAIF_B CP SMS SAIF_L RP MAXPAIFR X WL SAIF_FMT [1:0] DAC2SEL[1:0] CPY_N PLLPD
101111110 100001101 000000011 011100100 000000000 000000000 000000000 000110001 000001011 000100010 000000010
DAC1SEL[1:0] AUDIO_N CON/PRO
ORGSAMP[3:0]
SAIFRATE[2:0]
R64(40h)
1
0
0
0
0
0
0
ALWAYSVA FILLMODE LID SAIFSRC[1:0]
RXINSEL[1:0]
0
0
0
SPDINMODE
000000000
R65(41h)
1
0
0
0
0
0
1
PAIFSRC[1:0]
TXRXT HRU
TXSRC[1:0]
RX2DAC
000010000
R66(42h) R67(43h) R68(44h) R69(45h) R70(46h) R71(47h) R72(48h) R73(49h)
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1
0 0 1 1 1 1 0 0
1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
0
0
0
FPLL[2:0] Reserved Reserved Reserved Reserved
0
0
0
000111000 00000000 000000000 000000000 000000000
0 0 0
GPIO2OP[3:0] GPOMODEOP[3:0] MASK[7:0]
GPIO1OP[3:0] GPIO3OP[3:0]
000010000 010100010 000000000
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PP Rev 1.94 November 2004 74
Product Preview
REGISTER B15 B14 B13 B12 R74(4Ah) R75(4Bh) R76(4Ch) R77(4Dh) R78(4Eh) R79(4Fh) R80(50h) R81(51h) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 B11 B10 0 0 1 1 1 1 0 0 1 1 1 0 0 1 1 0 0 1 B9 0 1 0 1 0 1 0 1 1 B8 0 0 B7 0 SPDIF_MO DE B6 0 CPY_N B5 READEN2 PCM_N B4
READEN 3 AUDIO_N
WM8777
B3 0 BIP B2 0
PARITYERR
B1 0
VALIDITY
B0 0 UNLOCK
DEFAULT 000000000
Read Only 1 Read Only 2 Read Only 3 Read Only 4 Read Only 5 Read Only 6 RESET DATA See Notes DEFAULT
R127(7Fh) 1
ADDRESS
Table 81 Register Map Note: Any write to R127 causes a software reset.
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PP Rev 1.94 November 2004 75
WM8777
Product Preview
REGISTER ADDRESS 0000000 (00h) Analogue Attenuation FRONTL
BIT 6:0
LABEL FRONTLA[6:0]
DEFAULT 1101011 (0dB) 0
DESCRIPTION Analogue Attenuation control for FRONTL in 1dB steps. See Table 60. FRONTL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store FRONTL in intermediate latch (no change to output) 1 = Store FRONTL and update attenuation on all channels. Analogue Attenuation control for FRONTR in 1dB steps. See Table 60. FRONTR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store FRONTR in intermediate latch (no change to output) 1 = Store FRONTR and update attenuation on all channels. Analogue Attenuation control for CNTR in 1dB steps. See Table 60. CNTR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store CNTR in intermediate latch (no change to output) 1 = Store CNTR and update attenuation on all channels. Analogue Attenuation control for LFE in 1dB steps. See Table 60. LFE zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store LFE in intermediate latch (no change to output) 1 = Store LFE and update attenuation on all channels. Analogue Attenuation control for SURL in 1dB steps. See Table 60. SURL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store SURL in intermediate latch (no change to output) 1 = Store SURL and update attenuation on all channels. Analogue Attenuation control for SUR Right in 1dB steps. Table 60. SURR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store SURR in intermediate latch (no change to output) 1 = Store SURR and update attenuation on all channels.
7
FRONTLZCEN
8
UPDATE
Not latched
0000001 (01h) Analogue Attenuation FRONTR
6:0
FRONTRA[6:0]
1101011 (0dB) 0
7
FRONTRZCEN
8
UPDATE
Not latched
0000010 (02h) Analogue Attenuation CNTR
6:0 7
CNTRA[6:0] CNTRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0000011 (03h) Analogue Attenuation LFE
6:0 7
LFEA[6:0] LFEZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0000100 (04h) Analogue Attenuation SURL
6:0 7
SURLA[6:0] SURLZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0000101 (05h) Analogue Attenuation SURR
6:0 7
SURRA[6:0] SURRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
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PP Rev 1.94 November 2004 76
Product Preview REGISTER ADDRESS 0000110 (06h) Analogue Attenuation AUXL BIT 6:0 7 LABEL AUXLA[6:0] AUXLZCEN DEFAULT 1101011 (0dB) 0 DESCRIPTION
WM8777
Analogue Attenuation control for AUXL in 1dB steps. See Table 60. AUXL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store AUXL in intermediate latch (no change to output) 1 = Store AUXL and update attenuation on all channels. Analogue Attenuation control for AUXR in 1dB steps. See Table 60. AUXR zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store AUXR in intermediate latch (no change to output) 1 = Store AUXR and update attenuation on all channels. Analogue Attenuation control for HPHONEL in 1dB steps. See Table 60. HPHONEL zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store HPHONEL in intermediate latch (no change to output) 1 = Store HPHONEL and update attenuation on all channels. Analogue Attenuation control for HPHONER in 1dB steps. See Table 60. HPHONER zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store HPHONER in intermediate latch (no change to output) 1 = Store HPHONER and update attenuation on all channels. Analogue Attenuation control for all DAC gains in 1dB steps. See Table 60. Master zero cross detect enable 0 = zero cross disabled 1 = zero cross enabled Controls simultaneous update of all Analogue Attenuation Latches 0 = Store gains in intermediate latch (no change to output) 1 = Store gains and update attenuation on all channels. Digital Attenuation control for DAC1 Left Channel (LSUMOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA1 in intermediate latch (no change to output) 1 = Store LDA1 and update attenuation on all channels Digital Attenuation control for DAC1 Right Channel (RSUMOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA1 in intermediate latch (no change to output) 1 = Store RDA1 and update attenuation on all channels. Digital Attenuation control for DAC2 Left Channel (CNTSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA2 in intermediate latch (no change to output) 1 = Store LDA2 and update attenuation on all channels.
8
UPDATE
Not latched
0000111 (07h) Analogue Attenuation AUXR
6:0 7
AUXRA[6:0] AUXRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0001000 (08h) Analogue Attenuation HPHONEL
6:0 7
HPLA[6:0] HPLZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0001001 (09h) Analogue Attenuation HPHONER
6:0 7
HPRA[6:0] HPRZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0001010 (0Ah) Analogue Attenuation Master (all channels)
6:0 7
MASTA[6:0] MZCEN
1101011 (0dB) 0
8
UPDATE
Not latched
0001011 (0Bh) Digital Attenuation DACL1 0001100 (0Ch) Digital Attenuation DACR1 0001101 (0Dh) Digital Attenuation DACL2
7:0 8
LDA1[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
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PP Rev 1.94 November 2004 77
WM8777
REGISTER ADDRESS 0001110 (0Eh) Digital Attenuation DACR2 0001111 (0Fh) Digital Attenuation DACL3 0010000 (10h) Digital Attenuation DACR3 0010001 (11h) Digital Attenuation DACL4 0010010 (12h) Digital Attenuation DACR4 0010011 (13h) Digital Attenuation Master (all channels) 0010100 (14h) DAC Output Phase BIT 7:0 8 LABEL RDA2[7:0] UPDATE DEFAULT 11111111 (0dB) Not latched DESCRIPTION
Product Preview
Digital Attenuation control for DAC2 Right Channel (LFESOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA2 in intermediate latch (no change to output) 1 = Store RDA2 and update attenuation on all channels. Digital Attenuation control for DAC3 Left Channel (LSURSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA3 in intermediate latch (no change to output) 1 = Store LDA3 and update attenuation on all channels. Digital Attenuation control for DAC3 Right Channel (RSURSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA3 in intermediate latch (no change to output) 1 = Store RDA3 and update attenuation on all channels. Digital Attenuation control for DAC4 Left Channel (LAUXSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store LDA4 in intermediate latch (no change to output) 1 = Store LDA4 and update attenuation on all channels. Digital Attenuation control for DAC4 Right Channel (RAUXSOP) in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store RDA4 in intermediate latch (no change to output) 1 = Store RDA4 and update attenuation on all channels. Digital Attenuation control for all DAC channels in 0.5dB steps. See Table 63 Controls simultaneous update of all Attenuation Latches 0 = Store gain in intermediate latch (no change to output) 1 = Store gain and update attenuation on all channels. Controls phase of DAC outputs PHASE[0] = 1 inverts phase of DAC1L output PHASE[1] = 1 inverts phase of DAC1R output PHASE[2] = 1 inverts phase of DAC2L output PHASE[3] = 1 inverts phase of DAC2R output PHASE[4] = 1 inverts phase of DAC3L output PHASE[5] = 1 inverts phase of DAC3R output PHASE[6] = 1 inverts phase of DAC4L output PHASE[7] = 1 inverts phase of DAC4R output DAC Digital Volume Zero Cross Enable: 0 = Zero Cross detect disabled 1 = Zero Cross detect enabled Attenuator Control 0 = All DACs use attenuations as programmed. 1 = Right channel DACs use corresponding left DAC attenuations Infinite zero detection circuit control and automute control 0 = Infinite zero detect automute disabled 1 = Infinite zero detect automute enabled DAC Analogue Zero cross detect timeout disable 0 = Timeout enabled 1 = Timeout disabled
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
LDA4[7:0] UPDATE
11111111 (0dB) Not latched
7:0 8
RDA4[7:0] UPDATE
11111111 (0dB) Not latched
7:0
MASTDA[7:0]
11111111 (0dB) Not latched
8
UPDATE
7:0
PHASE[7:0]
00000000
0010101 (15h) DAC Attenuation Control
0
DZCEN
0
1
DACATC
0
2
IZD
0
4
TOCDAC
0
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PP Rev 1.94 November 2004 78
Product Preview REGISTER ADDRESS BIT 8:5 LABEL PL[3:0] DEFAULT 1001 DAC Output Control PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 0010110 (16h) Mute Control 3:0 DMUTE[3:0] 0000 Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left PL[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION
WM8777
Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2
Right Output Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
DAC channel soft mute enables: DMUTE[0] = 1, enable softmute on DAC1. DMUTE[1] = 1, enable softmute on DAC2. DMUTE[2] = 1, enable softmute on DAC3. DMUTE[3] = 1, enable softmute on DAC4. DAC channel master soft mute. Mutes all DAC channels: 0 = disable softmute on all DACs. 1 = enable softmute on all DACs. RECL Output Enable 00 = REC output muted 01 = REC output ADCL 10 = REC output DAC1L RECR Output Enable 00 = REC output muted 01 = REC output ADCR 10 = REC output DAC1R De-emphasis mode select: DEEMPH[0] = 1, enable De-emphasis on DAC1. DEEMPH[1] = 1, enable De-emphasis on DAC2. DEEMPH[2] = 1, enable De-emphasis on DAC3. DEEMPH[3] = 1, enable De-emphasis on DAC4. Selects the ouput for ZFLG1 and ZFLG2 pins (see Table 53). 1 = indicates 1024 consecutive zero input samples on the channels selected 0 = indicates at least one of selected channels has non zero sample in last 1024 inputs
4
MUTEALL
0
6:5
RECLEN
00
8:7
RECREN
00
0010111 (17h) DAC Control
3:0
DEEMP[3:0]
0000
7:4
DZFM[3:0]
0000
0011000 (18h) Primary Interface Control (RX)
1:0
PAIFRX_FMT [1:0]
10
Interface format select
00 = right justified mode 01 = left justified mode 10 = I2S mode 11 = DSP (early or late) mode PDATAIPLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / I2S 0 =Standard PDATAIPLRC Polarity 1 =Inverted PDATAIPLRC Polarity DSP Mode 0 = Early DSP mode 1 = Late DSP mode
2
PAIFRX_LRP
0
3
PAIFRX_BCP
0
PBCLK Polarity 0 = Normal - DIN[3:0], PDATAIPLRC and PDATAOPLRC sampled on rising edge of PBCLK; PDATAOP changes on falling edge of PBCLK. 1 = Inverted - DIN[3:0], PDATAIPLRC and PDATAOPLRC sampled on falling edge of PBCLK; PDATAOP changes on rising edge of PBCLK.
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PP Rev 1.94 November 2004 79
WM8777
REGISTER ADDRESS BIT 5:4 LABEL PAIFRX_WL [1:0] DEFAULT 10 DESCRIPTION
Product Preview
Input Word Length 00 = 16-bit Mode 01 = 20-bit Mode 10 = 24-bit Mode 11 = 32-bit Mode (not supported in right justified mode) MCLK pin output enable 0 = MCLK pin is an input 1 = MCLK pin is an output (see MCLKOUTSRC below) MCLK pin output source 0 = PLL 1 = Crystal clock output. Master Mode MCLK:PDATAOPLRC ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs DAC oversample rate select: 0 = 128x oversampling 1 = 64x oversampling Master Mode MCLK:PDATAIPLRC ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Master/Slave Interface mode select. If ADCCLKSRC is set high then this register control whether the ADC clocks are in master or slave mode/ 0 = Slave Mode - PDATAOPLRC and ADCPBCLK are inputs 1 = Master Mode - PDATAOPLRC and ADCPBCLK are outputs Maser/Slave interface mode select 0 = Slave Mode - PDATAOPLRC, PDATAIPLRC and PBCLK are inputs 1 = Master Mode - PDATAOPLRC, PDATAIPLRC and PBCLK are outputs Note if ADCCLKSRC is set high then this register only controls PDATAIPLRC and PBCLK. Chip Powerdown Control (works in tandem with the other powerdown registers): 0 = All digital circuits running, outputs are active 1 = All digital circuits in power save mode, outputs muted ADC powerdown: 0 = ADC enabled 1 = ADC disabled DAC powerdowns (0 = DAC enabled, 1 = DAC disabled) DACPD[0] = DAC1 DACPD[1] = DAC2 DACPD[2] = DAC3 DACPD[3] = DAC4
6
MCLKOPEN
0
7
MCLKOUTSRC
0
0011001 (19h) Master Mode Control
2:0
PAIFTX_RATE [2:0]
010
3
DACOSR
0
6:4
PAIFRX_RATE [2:0]
010
7
PAIFTX_MS
0
8
PAIFRX_MS
0
0011010 (1Ah) Powerdown Control
0
PWDN
0
1
ADCPD
1
5:2
DACPD[3:0]
1111
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PP Rev 1.94 November 2004 80
Product Preview REGISTER ADDRESS BIT 6 LABEL SPDIFTXD DEFAULT 1 DESCRIPTION SPDIF_TX powerdown 0 = SPDIF_TX enabled 1 = SPDIF_TX disabled SPDIF_RX powerdown 0 = SPDIF_RX enabled 1 = SPDIF_RX disabled OSC power down 0 = Oscillator enabled 1 = Oscillator disabled
WM8777
7
SPDIFRXD
1
8
OSCPD
1
0011011 (1Bh) Primary Interface Control (TX)
1:0
PAIFTX_FMT
10
Interface format select
00 = right justified mode 01 = left justified mode 10 = I2S mode 11 = DSP (early or late) mode PDATAOPLRC Polarity or DSP Early/Late mode select Left Justified / Right Justified / I2S 0 =Standard PDATAOPLRC Polarity 1 =Inverted PDATAOPLRC Polarity DSP Mode 0 = Early DSP mode 1 = Late DSP mode
[1:0]
2
PAIFTX_LRP
0
3
PAIFTX_BCP
0
ADCPBCLK/PBCLK Polarity 0 = Normal ADCPBCLK/PBCLK. 1 = Inverted ADCPBCLK/PBCLK. Input Word Length 00 = 16-bit Mode 01 = 20-bit Mode 10 = 24-bit Mode 11 = 32-bit Mode (not supported in right justified mode) ADC Highpass Filter Disable: 0 = Highpass Filter enabled 1 = Highpass Filter disabled ADC oversample rate select 0 = 128x oversampling 1 = 64x oversapmling Sync ADC and DAC together. 0 = Enable SYNC function 1 = Disable Sync function Limiter threshold/ALC target level in 1dB steps. 0000: -16dB FS 0001: -15dB FS ... 1101: -3dB FS 1110: -2dB FS 1111: -1dB FS Set Maximum Gain of PGA 111 = +24dB 110 = +20dB ....(-4dB steps) 010 = +4dB 001 = 0dB 000 = 0dB ALC/Limiter function select 00 = Limiter 01 = ALC Right channel only 10 = ALC Left channel only 11 = ALC Stereo (PGA registers unused) PP Rev 1.94 November 2004 81
5:4
PAIFTX_WL
10
[1:0]
6
ADCHPD
0
7
ADCOSR
0
8
SYNC
0
0011101 (1Dh) ALC Control 1
3:0
LCT[3:0]
1011 (-6dB)
6:4
MAXGAIN[2:0]
111 (+24dB)
8:7
LCSEL[1:0]
00 (OFF)
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WM8777
REGISTER ADDRESS 0011110 (1Eh) ALC Control 2 BIT 3:0 LABEL HLD[3:0] DEFAULT 0000 (0MS) DESCRIPTION ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC zero cross detection circuit. 0 = Zero cross detection disabled. 1 = Zero cross detection enabled. Enable the PGA gain control circuit. 0 = PGA gain control disabled 1 = PGA gain control enabled ALC/Limiter attack (gain ramp down) time ACL mode 0000 = 8.4ms 0001 = 16.8ms 0010 = 33.6ms.. (time doubles with every step) 1010 or higher = 8.6s ACL mode 0000 = 33.5ms 0001 = 67.2ms 0010 = 134.4ms.. (time doubles with every step) 1010 or higher = 34.41s 8 FDECAY 0
Product Preview
7
ALCZC
0
8
LCEN
0
0011111 (1Fh) ALC Control 3
3:0
ATK[3:0]
0010 (33ms/1ms)
Limiter mode 0000 = 250us 0001 = 500us 0010 = 1ms (time doubles with every step) 1010 or higher = 256ms Limiter mode 0000 = 1.2ms 0001 = 2.4ms 0010 = 4.8ms (time doubles with every step) 1010 or higher = 1.2288s
7:4
DCY[3:0]
0011
ALC/Limiter decay (gain ramp up) time
Frequency dependant decay enable (Limiter only) 0 = Frequency dependent decay disabled 1 = Frequency dependent decay enabled DCY 0000 0001 0010 ..... 1010 or higher 20KHz input (or disabled) 1.2ms 2.4ms 4.8ms ..... 1.2288s 1KHz input 24ms 48ms 96ms ..... 24.576s
0100000 (20h) Noise Gate Control
0
NGAT
0
Noise gate enable (ALC only) 0 = Noise gate disabled 1 = Noise gate enabled Noise gate threshold 000 = -78dBFS 001 = -72dBfs ... 6 dB steps 110 = -42dBFS 111 = -36dBFS Maximum attenuation of PGA ALC (lower PGA gain limit) 1010 or lower = -1dB 1011 = -5dB ...... (-4dB steps) 1110 = -17dB 1111 = -21dB Limiter (attenuation below static) 0000 = -3dB 0001 = -4dB 0010 = -5dB .... (-1dB steps) 1001 = -12dB
4:2
NGTH[2:0]
000
0100001 (21h) Limiter Control
3:0
MAXATTEN [3:0]
0110
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PP Rev 1.94 November 2004 82
Product Preview REGISTER ADDRESS BIT 6:4 LABEL TRANWIN [2:0] DEFAULT 010 DESCRIPTION Length of Transient Window 000 = 0us (disabled) 001 = 62.5us 010 = 125us ..... 111 = 4ms Control treble boost and cut:00 = both off ( Amps disabled) 01 = Treble cut 10 = Treble boosted 11 = both off (Amps enabled) Controls bass boost and cut:00 = both off (Amps disabled) 01 = Bass cut 10 = Bass boosted 11 = both off (Amps enabled) Bass managed signal path select 0 = Path disabled 1 = Path enabled Bypass signal path select 0 = Path disabled 1 = Path enabled 0 = AIN6 not selected 1 = AIN6 applied to FRONT channels Front LFE gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB LFE signal path select 0 = Path disabled 1 = Path enabled Front CNTR gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB Center signal path mix 0 = Path disabled 1 = Path enabled Front REAR gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB
WM8777
0100010 (22h) FRONT Mixer Control 1
1:0
FTRBL[1:0]
00
3:2
FBASS[1:0]
00
4
FBM
0
5
FBYP
0
6 0100011 (23h) FRONT Mixer Control 2 2:0
AIN6 FLFEGAIN[2:0]
0 000
3
FLFE
0
6:4
CNTRGAIN[2:0]
000
7
CNTR
0
0100100 (24h) FRONT Mixer Control 3
2:0
REARGAIN[2:0]
000
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PP Rev 1.94 November 2004 83
WM8777
REGISTER ADDRESS BIT 3 LABEL REAR DEFAULT 0 Rear signal path mix 0 = Path disabled 1 = Path enabled Control treble boost and cut: 00 = both off (Amps disabled) 01 = Treble cut 10 = Treble boosted 11 = both off (Amps enabled) Controls bass boost and cut:00 = both off (Amps disabled) 01 = Bass cut 10 = Bass boosted 11 = both off (Amps enabled) Bass managed signal path select 0 = Path disabled 1 = Path enabled Bypass signal path select 0 = Path disabled 1 = Path enabled Controls headphone output MUX:0 = FRONTL/R output on headphone channels 1 = AUXL/R output on headphone channels Center LFE gain: 000 = 0dB 001 = 1dB 010 = 2dB 011 = 3dB 100 = 4dB 101 = 4.5dB 110 = 5dB 111 = 6dB LFE signal path select: 0 = Path disabled 1 = Path enabled Bypass select for AUX left output 0 = Bass managed 1 = Bypass Bypass select for AUX right output 0 = Bass managed 1 = Bypass Bypass select for surround left output 0 = Bass managed 1 = Bypass Bypass select for surround right output 0 = Bass managed 1 = Bypass Gain control for Bass boost/cut - see table 3 DESCRIPTION
Product Preview
0100101 (25h) Center Mixer Control 1
1:0
CTRBL[1:0]
00
3:2
CBASS[1:0]
00
4
CBM
0
5
CBYP
0
6
HPSEL
0
0100110 (26h) Center Mixer Control 2
2:0
CLFEGAIN[2:0]
000
3
CLFE
0
0100111 (27h) Bass Management Bypass
0
AUXLBYP
0
1
AUXRBYP
0
2
SURLBYP
0
3
SURRBYP
0
0101000 (28h) Front Bass Control
3:0 8
FBASS[3:0] UPDATE
0000 Not latched
Controls simultaneous update of all Attenuation Latches 0 = Store GAIN FRONT BASS in intermediate latch (no change to output) 1 = Store GAIN FRONT BASS and update attenuation on all channels. Gain control for Bass boost/cut - see table 3
0101001
3:0
FTREB[3:0]
0000
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PP Rev 1.94 November 2004 84
Product Preview REGISTER ADDRESS (29h) Front Treble Control BIT 8 LABEL UPDATE DEFAULT Not latched DESCRIPTION
WM8777
Controls simultaneous update of all Attenuation Latches 0 = Store GAIN FRONT TREBLE in intermediate latch (no change to output) 1 = Store GAIN FRONT TREBLE and update attenuation on all channels. Gain control for Bass boost/cut - see table 3 Controls simultaneous update of all Attenuation Latches 0 = Store GAIN CENTER BASS in intermediate latch (no change to output) 1 = Store GAIN CENTER BASS and update attenuation on all channels. Gain control for Bass boost/cut - see table 3 Controls simultaneous update of all Attenuation Latches 0 = Store GAIN CENTER TREBLE in intermediate latch (no change to output) 1 = Store GAIN CENTER TREBLE and update attenuation on all channels. PREGAIN control for CNTR control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation PREGAIN control for FRONTR tone control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation PREGAIN control for FRONTL tone control channel 00 = 0dB Attenuation 01 = -6dB Attenuation 10 = -12dB Attenuation 11 = -18dB Attenuation Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN CNTR in intermediate latch (no change to output) 1 = Store PREGAIN CNTR and update attenuation on all channels. Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN RIGHT in intermediate latch (no change to output) 1 = Store PREGAIN RIGHT and update attenuation on all channels. Controls simultaneous update of all Attenuation Latches 0 = Store PREGAIN LEFT in intermediate latch (no change to output) 1 = Store PREGAIN LEFT and update attenuation on all channels. Auxiliary left output powerdown. 0 = powerup 1 = powerdown Auxiliary left output powerdown. 0 = powerup 1 = powerdown Surround left output powerdown. 0 = powerup 1 = powerdown
0101010 (2Ah) Center Bass Control
3:0 8
CBASS[3:0] UPDATE
0000 Not latched
0101011 (2Bh) Center Treble Control
3:0 8
CTREB[3:0] UPDATE
0000 Not latched
0101100 (2Ch) Mixer Pregain
1:0
CNTP[1:0]
00
3:2
FTRP[1:0]
00
5:4
FTLP[1:0]
00
6
UPDATEC
0
7
UPDATER
0
8
UPDATEL
0
0101101 (2Dh) Output Powerdown
0
AUXLPD
1
1
AUXRPD
1
2
SURLPD
1
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WM8777
REGISTER ADDRESS BIT 3 LABEL SURRPD DEFAULT 1 DESCRIPTION Surround Right output powerdown. 0 = powerup 1 = powerdown LFE output powerdown. 0 = powerup 1 = powerdown Center output powerdown. 0 = powerup 1 = powerdown Front Left output powerdown. 0 = powerup 1 = powerdown Front Right output powerdown. 0 = powerup 1 = powerdown Headphone output powerdown. 0 = powerup 1 = powerdown
Product Preview
4
LFEPD
1
5
CTRPD
1
6
FRTLPD
1
7
FRTRPD
1
8
HPPD
1
0101110 (2Eh) Attenuation ADC Left 0101111 (2Fh) Attenuation ADC Right 0110000 (30h) Attenuation Control
7:0 8
LAG[7:0] ZCLEN
11001111 (0dB) 0
Attenuation control for left channel ADC gain in 0.5dB steps. See Table 68 Zero Cross enable for left channel ADC 0 = Disable Zero Cross 1 = Enable Zero Cross Attenuation control for right channel ADC gain in 0.5dB steps. See Table 68 Zero Cross enable for right channel ADC 0 = Disable Zero Cross 1 = Enable Zero Cross Left Channel mute control 0 = Channel not muted 1 = Channel muted Left Channel mute control 0 = Channel not muted 1 = Channel muted Attenuator Control 0 = ADC use attenuations as programmed. 1 = Right channel ADC use corresponding left ADC attenuations Time out clock enable/disable 0 = Time out clock enabled. 1 = Time out clock disabled.
7:0 8
RAG[7:0] ZCREN
11001111 (0dB) 0
0
MUTEL
0
1
MUTER
0
2
ADCATC
0
3
TOADC
0
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Product Preview REGISTER ADDRESS 0110001 (31h) ADC Mux and Powerdown Control BIT 5:0 LABEL AIN[5:0] DEFAULT 00000 DESCRIPTION
WM8777
ADC left channel input mux control bits 00000 = UTE 00001 = AIN1 00010 = AIN2 00011 = AIN1 + AIN2 ...... 11111 = AIN1 + AIN2 + AIN3 + AIN4 + AIN5 + AIN6 Input mux and buffer powerdown 0 = Input mux and buffer enabled 1 = Input mux and buffer powered down VOUT1 Output select (see Figure 28) VOUT2 Output select (see Figure 28) Mixer Powerdown select 0 = Powerup 1 = Powerdown Mixer Powerdown select 0 = Powerup 1 = Powerdown VOUT3 Output select (see Figure 28) VOUT4 Output select (see Figure 29) Mixer Powerdown select 0 = Powerup 1 = Powerdown Mixer Powerdown select 0 = Powerup 1 = Powerdown Fractional (K) part of PLL input/output frequency ratio (bits 8:0).
8
AINPD
1
0110010 (32h) Output Mux and Powerdown Control 1
2:0 5:3 7
MX1[2:0] MX2[2:0] OUTPD1
001 001 1
8
OUTPD2
1
0110011 (33h) Output Mux and Powerdown Control 2
2:0 4:3 7
MX3[2:0] MX4[1:0] OUTPD3
001 01 1
8
OUTPD4
1
0110100 (34h) PLL Control 1 0110101 (35h) PLL Control 2 0110110 (36h) PLL Control 3
8:0
PLL_K[8:0]
121 (Hex)
8:0
PLL_K[17:9]
17E (Hex)
Fractional (K) part of PLL input/output frequency ratio (bits 17:9).
3:0 4
PLL_K[21:18] CLKOUTSRC
D(Hex) 0
Fractional (K) part of PLL input/output frequency ratio (bits 21:18) CLKOUT pin source:0 = PLL clock output 1 = Crystal clock output. DAC clock source 0 = MCLK pin 1 = PLL clock ADC clock source 0 = MCLK or ADCMLCK pin 1 = PLL clock S/PDIF TX clock source 0 = MLCK or ADCMCLK pin 1 = PLL clock 0 = Enable PLL 1 = Disable PLL 0 = no post scale 1= divide MCLK by 2 after PLL 0 = Integer N only PLL 1 = Integer N and Fractional K PLL 0 = no pre-scale 1 = divide MCLK by 2 prior to PLL Integer (N) divisor part of PLL input/output frequency ratio. Use values greater than 5 and less than 13.
6
PLL2DAC
0
7
PLL2ADC
0
8
PLL2TX
1
0110111 (37h) PLL Control 4
0 1 2 3 8:4
PLLPD POSTSCALE FRAC_EN PRESCALE PLL_N[4:0]
1 0 0 0 00000
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WM8777
REGISTER ADDRESS 0111000 (38h) DAC Digital Input Selector 0111001 (39h) S/PDIF Transmitter Channel Bit Control 1 BIT 1:0 3:2 5:4 7:6 0 1 2 5:3 LABEL DAC1SEL[1:0] DAC2SEL[1:0] DAC3SEL[1:0] DAC4SEL[1:0] CON/PRO AUDIO_N CPY_N PREEMPH[2:0] DEFAULT 00 01 10 11 0 0 0 000 DESCRIPTION DAC digital input select. 00 = DAC takes data from 01 = DAC takes data from 10 = DAC takes data from 11 = DAC takes data from
Product Preview
PDATAIP1 PDATAIP2 PDATAIP3 PDATAIP4
0 = Consumer Mode 1 = Professional Mode (not supported by WM8777) 0 = S/PDIF transmitted data is audio PCM. 1 = S/PDIF transmitted data is not audio PCM. 0 = Transmitted data has copyright asserted. 1 = Transmitted data has no copyright assertion. 000 = Data from Audio interface has no pre-emphasis. 001 = Data from Audio interface has pre-emphasis. 010 = Reserved (Audio interface has pre-emphasis). 011 = Reserved (Audio interface has pre-emphasis). All other modes are reserved and should not be used. S/PDIF Channel status bits. 00 = Only valid mode for consumer applications. All other modes are reserved. Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode.
7:6
CHSTMODE[1:0]
00
0111010 (3Ah) S/PDIF Transmitter Channel Bit Control 2 0111011 (3Bh) S/PDIF Transmitter Channel Bit Control 3
7:0
CATCODE[7:0]
00000000
3:0 5:4
SRCNUM[3:0] CHNUM1[1:0]
0000 00
Source Number. No definitions are attached to data. See S/PDIF specification for details. Channel Number for Subframe 1 CHNUM1 00 01 10 11 Channel Status Bits[23:20] 0000: Do not use channel number 0001: Send to Left Channel 0010: Send to Right Channel 0000: Do not use channel number
7:6
CHNUM2[1:0]
00
Channel Number for Subframe 2 CHNUM2 00 01 10 11 Channel Status Bits[23:20] 0000: Do not use channel number 0001: Send to Left Channel 0010: Send to Right Channel 0000: Do not use channel number
0111100 (3Ch) S/PDIF Transmitter Channel Bit Control 4
3:0 5:4
FREQ[3:0] CLKACU[1:0]
0001 11
Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated. Clock Accuracy of Generated clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. Maximum Audio sample word length 0 = 20 bits 1 = 24 bits
0111101 (3Dh) S/PDIF
0
MAXPAIFRX_WL
1
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Product Preview REGISTER ADDRESS BIT 3:1 LABEL TXPAIFRX_WL [2:0] DEFAULT 101 DESCRIPTION Audio Sample Word Length. 000 = Word Length Not Indicated TXPAIFRX_WL 001 010 100 101 110 7:4 ORGSAMP[3:0] 0000 MAXPAIFRX_WL= =1 20 bits 22 bits 23 bits 24 bits 21 bits
WM8777
MAXPAIFRX_WL= =0 16 bits 18 bits 19 bits 20 bits 17 bits
All other combinations reserved Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated Secondary Audio Interface format select 00 = right justified mode 01 = left justified mode 10 = IS mode 11 = DSP (early or late) mode SLRCLK Polarity or DSP Early/Late mode select Left Justified / Right Justified/ I2S 0 = Standard PDATAIPLRC Polarity 1 = Inverted PDATAIPLRC Polarity 3
SAIF_BCP
0111110 (3Eh) Secondary Interface Control
1:0
SAIF_FMT
10
[1:0]
2
SAIF_LRP
0
DSP Mode 0 = Early DSP mode 1 = Late DSP mode
0
SPBCLK Polarity 0 = Normal SPBCLK. 1 = Inverted SPBCLK. Input Word Length 00 = 16-bit Mode 01 = 20-bit Mode 10 = 24-bit Mode 11 = 32-bit Mode (not supported in right justified mode) Master Mode MCLK:SLRC ratio select: 000 = 128fs 001 = 192fs 010 = 256fs 011 = 384fs 100 = 512fs 101 = 768fs 110 = 1152fs Maser/Slave interface mode select 0 = Slave Mode - SLRC and SPBCLK are inputs 1 = Master Mode - SLRC and SPBCLK are outputs Audio interface master clock source when SMS is 1. 00 = MCLK 01 = GPIO (If ADCCLKSRC is set) 10 = PLL clock 11 = PLL clock Selects the input circuit type for the S/PDIF input 0 = Normal CMOS input 1 = Comparator input. Compatible with 200mV AC coupled consumer S/PDIF input signals.
5:4
SAIF_WL
10
[1:0]
0111111 (3Fh) Secondary Interface Master Mode Control
2:0
SAIFRATE[2:0]
010
3
SMS
0
5:4
SAIFCLKSRC[1:0]
00
1000000 (40h) S/PDIF Receiver
0
SPDINMODE
0
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WM8777
REGISTER ADDRESS Input Selector BIT 5:4 LABEL RXINSEL[1:0] DEFAULT 00 DESCRIPTION
Product Preview
S/PDIF Receiver input mux select. Note that the general purpose inputs must be configured using GPIOxOP to be either CMOS or comparator inputs if selected by RXINSEL. 00 = S/PDIF_IN1 01 = S/PDIF_IN2 (GPIO1) 10 = S/PDIF_IN3 (GPIO2) 11 = S/PDIF_IN4 (GPIO3) Determines what SPDIF_RX should do if the validity bit indicates invalid data: 0 = Data from SPDIF_RX remains static at last valid sample. 1 = Data from SPDIF_RX is output as all zeros. Used to override the recovered validity bit. 0 = Use validity bit. 1 = Ignore validity bit. ADC clock source 0 = ADCMCLK is from MCLK pin and ADCPBCLK is from PBCLK pin 1 = ADCMCLK is from GPIO1, and ADPBCLK is from GPIO2. (Note that when in this mode RXINSEL must not be set to 01 or 10.) Received S/PDIF PCM data to DAC. 0 = DAC1 takes data from Primary Audio Interface. 1 = DAC1 takes data from S/PDIF receiver. S/PDIF Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Secondary Audio Interface received data 11 = DAC Audio Interface Received data. Only used if TXSRC==00. Configures only the Channel Bit in the S/PDIF frame. 0 = Channel data equal to recovered channel data. 1 = Channel data taken from channel status registers. Audio Interface output source 00 = S/PDIF received data 01 = ADC digital output data 10 = Secondary Audio Interface received data 11 = Power-down Primary Audio Interface Transmitter Secondary Audio Interface Transmitter Data Source. 00 = S/PDIF received data. 01 = ADC digital output data. 10 = Power-down Secondary Audio Interface Transmitter 11 = Primary Audio Interface received data. Select jitter attenuation bandwidth. 000 = Invalid 001 = 28.84Hz 010 = 14.92Hz 011 = 7.46Hz 100 = 3.73Hz 101 = 1.87Hz 110 = 0.97Hz 111 = 0.47Hz
6
FILLMODE
0
7
ALWAYSVALID
0
8
ADCCLKSRC
0
1000001 (41h) Interface Source Select
0
RX2DAC
0
2:1
TXSRC[1:0]
00
3
TXRXTHRU
0
5:4
PAIFSRC[1:0]
01
7:6
SAIFSRC[1:0]
00
1000010 (42h) S/PDIF Data/Clock Recovery
5:3
FPLL[2:0]
111
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Product Preview REGISTER ADDRESS 1000111 (47h) GPIO Control 1 BIT 3:0 LABEL GPIO1OP[3:0] DEFAULT 0000 DESCRIPTION
WM8777
0000 = INT 0001 = V - Validity 0010 = U - User Data bit 0011 = C - Channel Status Data 0100 = P - Parity bit 0101 = Non-audio (AUDIO_N || PCM_N) 0110 = UNLOCK 0111 = CSUD (Channel Status Registers Updated) 1000 = Zero Flag 1 output 1001 = Zero Flag 2 output 1010 = GPIO1set as S/PDIF input (standard CMOS input buffer) 1011 = GPIO1set as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals) 1100 = Sub Frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = Start of Block signal 0000 = INT 0001 = V - Validity 0010 = U - User Data bit 0011 = C - Channel Status Data 0100 = P - Parity bit 0101 = Non-audio (AUDIO_N || PCM_N) 0110 = UNLOCK 0111 = CSUD (Channel Status Registers Updated) 1000 = Zero Flag 1 output 1001 = Zero Flag 2 output 1010 = GPIO2set as S/PDIF input (standard CMOS input buffer) 1011 = GPIO2set as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals) 1100 = Sub Frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = Start of Block signal 0000 = INT 0001 = V - Validity 0010 = U - User Data bit 0011 = C - Channel Status Data 0100 = P - Parity bit 0101 = Non-audio (AUDIO_N || PCM_N) 0110 = UNLOCK 0111 = CSUD (Channel Status Registers Updated) 1000 = Zero Flag 1 output 1001 = Zero Flag 2 output 1010 = GPIO3set as S/PDIF input (standard CMOS input buffer) 1011 = GPIO3set as S/PDIF input (`comparator' input for AC coupled consumer S/PDIF signals) 1100 = Sub Frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = Start of Block signal
7:4
GPIO2OP[3:0]
0001
1001000 (48h) GPIO Control 2
3:0
GPIO3OP[3:0]
0010
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REGISTER ADDRESS BIT 7:4 LABEL GPOMODEOP [3:0] DEFAULT 1010 DESCRIPTION
Product Preview
0000 = INT 0001 = V - Validity 0010 = U - User Data bit 0011 = C - Channel Status Data 0100 = P - Parity bit 0101 = Non-audio (AUDIO_N || PCM_N) 0110 = UNLOCK 0111 = CSUD (Channel Status Registers Updated) 1000 = Zero Flag 1 output 1001 = Zero Flag 2 output 1010 = not used 1011 = not used 1100 = Sub Frame clock (1 = sub-frame1, 0 = sub-frame2) 1101 = Start of Block signal When a lag is masked, it does not update the Error Register or contribute to the interrupt pulse. 0 = unmask, 1 = mask. MASK[0] = mask control for UNLOCK MASK[1] = mask control for VALIDITY MASK[2] = mask control for PARITYERR MASK[3] = mask control for BIP MASK[4] = mask control for AUDIO_N MASK[5] = mask control for PCM_N MASK[6] = mask control for CPY_N MASK[7] = mask control for SPDIF_MODE 3-Wire Read-back mode enable. 0 = 3-Wire read-back mode disabled 1 = 3-Wire read-back mode enabled 2-Wire Read-back mode enable. 0 = 2-Wire read-back mode disabled 1 = 2-Wire read-back mode enabled PLL Unlock signal. 0 = PLL is locked to incoming S/PDIF stream. 1 = PLL is not locked to the incoming S/PDIF stream. V bit from S/PDIF input stream. 0 = Data word is valid. 1 = Data word is not valid. Even Parity check. 0 = No Parity errors detected. 1 = Parity error detected. Biphase coding of S/PDIF input stream. 0 = Biphase Coding is correct. 1 = Biphase Coding error detected. Received Channel status bit 1 has changed. 0 = Normal running. 1 = Change on AUDIO_N. PCM_N bit has changed 0 = Normal running. 1 = Change on PCM_N. Received Channel status bit 2 has changed. 0 = Normal running. 1 = Change on CPY_N.
1001001 (49h) S/PDIF Receiver Error Mask
7:0
MASK[7:0]
0000000
1001010 (4Ah) Read-back Control
4
READEN3
0
5
READEN2
0
1001011 (4Bh) S/PDIF Receiver Error Register (read-only)
0
UNLOCK
1
VALIDITY
2
PARITYERR
3
BIP
4
AUDIO_N
5
PCM_N
6
CPY_N
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PP Rev 1.94 November 2004 92
Product Preview REGISTER ADDRESS BIT 7 LABEL SPDIF_MODE DEFAULT DESCRIPTION S/PDIF mode change. 0: Normal running 1: Change in S/PDIF frequency mode detected.
WM8777
1001100 (4Ch) S/PDIF Receiver Channel Status Register 1 (read-only)
0
CON/PRO
Recovered S/PDIF Channel status bit 0. 0 = Consumer Mode 1 = Professional Mode The WM8777 is a consumer mode device. Detection of professional mode may give erroneous behavior. Recovered S/PDIF Channel status bit 1. 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Recovered S/PDIF Channel status bit 2. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Recovered S/PDIF Channel status bit 3. 0 = Recovered S/PDIF data has no pre-emphasis. 1 = Recovered S/PDIF data has pre-emphasis. Recovered S/PDIF Channel status bits[5:4]. Reserved for additional de-emphasis modes. Recovered S/PDIF Channel status bits[7:6]. 00 = Only valid mode for consumer applications. All other modes reserved. Recovered S/PDIF Channel status bits[15:8] - Category Code. Refer to S/PDIF specification for details. 00h indicates "general" mode.
1
AUDIO_N
2
CPY_N
3
DEEMPH
5:4 7:6
Reserved
CHSTMODE[1:0]
1001101 (4Dh) S/PDIF Receiver Channel Status Register 2 (read-only) 1001110 (4Eh) S/PDIF Receiver Channel Status Register 3 (read-only) 1001111 (4Fh) S/PDIF Receiver Channel Status Register 4 (read-only)
7:0
CATCODE[7:0]
3:0 7:4
SRCNUM[3:0] CHNUM1[3:0]
Recovered S/PDIF Channel status bits[19:16] - Indicates number of S/PDIF source. Recovered S/PDIF Channel status bits[23:20] - Channel number for channel 1. 0000 = Take no account of channel number (channel 1 defaults to left DAC) 0001 = channel 1 to left channel 0010 = channel 1 to right channel Recovered S/PDIF Channel status bits[27:24] - Sampling Frequency. See S/PDIF specification for details. 0001 = Sampling Frequency not indicated. Recovered S/PDIF Channel status bits[29:28] - Clock Accuracy of received clock. 00 = Level II 01 = Level I 10 = Level III 11 = Interface frame rate not matched to sampling frequency. Recovered S/PDIF Channel status bit[32] - Maximum Audio sample word length 0 = 20 bits 1 = 24 bits Recovered S/PDIF Channel status bits[35:33] - Audio Sample Word Length RXPAIFRX_WL 001 010 100 MAXPAIFRX_WL= =1 20 bits 22 bits 23 bits MAXPAIFRX_WL= =0 16 bits 18 bits 19 bits PP Rev 1.94 November 2004 93
3:0
FREQ[3:0]
5:4
CLKACU[1:0]
1010000 (50h) S/PDIF Receiver Channel Status Register 5 (read-only)
0
MAXPAIFRX_WL
3:1
RXPAIFRX_WL [2:0]
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WM8777
REGISTER ADDRESS BIT LABEL DEFAULT 101 110 DESCRIPTION 24 bits 21 bits
Product Preview
20 bits 17 bits
All other combinations are reserved and may give erroneous operation. 7:4 ORGSAMP[3:0] Recovered S/PDIF Channel status bits[39:36] - Original Sampling Frequency. See S/PDIF specification for details. 0000 = original sampling frequency not indicated Received Channel status bit 1 0 = Data word represents audio PCM samples. 1 = Data word does not represent audio PCM samples. Detects non-audio data from a 96-bit sync code, as defined in IEC-61937. 0 = Sync code not detected. 1 = Sync code detected - received data is not audio PCM. Recovered S/PDIF Channel status bit 2. 0 = Copyright is asserted for this data. 1 = Copyright is not asserted for this data. Note this signal is inverted and will cause an interrupt on logic 0. S/PDIF frequency mode. 00: Not supported 01: 88-96KHz 10: 44-48KHz 11: 32KHz Writing any value to this register will apply a reset to the device registers.
1010001 (51h) S/PDIF Status (readonly)
0
AUDIO_N
1
PCM_N
2
CPY_N
4:3
SPDIF_MODE
1111111 (7Fh) Software reset
8:0
RESET
Table 82 Register Map Description
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Product Preview
WM8777
DIGITAL FILTER CHARACTERISTICS
PARAMETER ADC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay DAC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay Table 83 Digital Filter Characteristics f > 0.555fs 0.555fs -60 16 dB fs 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs f > 0.5465fs 0.5465fs -65 22 dB fs 0.01 dB -6dB 0 0.5fs 0.01 dB 0.4535fs TEST CONDITIONS MIN TYP MAX UNIT
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB) Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 32 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 33 DAC Digital Filter Ripple - 44.1, 48 and 96kHz
0.2 0 0 -20
Response (dB) Response (dB)
-0.2
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 34 DAC Digital Filter Frequency Response (with DACOSR=1) - 192kHz
Figure 35 192kHz
DAC Digital filter Ripple (with DACOSR=1) -
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PP Rev 1.94 November 2004 95
WM8777
Product Preview
ADC HIGH PASS FILTER
The WM8777 has a selectable digital highpass filter to remove DC offsets. The filter response is characterised by the following polynomial.
H(z) =
1 - z-1 1 - 0.9995z-1
0
Response (dB)
-5
-10
-15
0
0.0005
0.001 Frequency (Fs)
0.0015
0.002
Figure 36 ADC Highpass Filter Response
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Product Preview
WM8777
1 0.5
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
-2 0
Response (dB) Response (dB)
-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 37 De-Emphasis Frequency Response (32kHz)
0
Figure 38 De-Emphasis Error (32KHz)
0.4 0.3
-2 0.2
Response (dB) Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 39 De-Emphasis Frequency Response (44.1KHz)
0
Figure 40 De-Emphasis Error (44.1KHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 41 De-Emphasis Frequency Response (48kHz)
Figure 42 De-Emphasis Error (48kHz)
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WM8777 APPLICATIONS INFORMATION
EXTERNAL ANALOGUE INPUT CIRCUIT CONFIGURATION
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In order to allow the use of 2V rms and larger inputs to the ADC and AUX inputs, a structure is used that uses external resistors to drop these larger voltages. This also increases the robustness of the circuit to external abuse such as ESD pulse. Figure 43 shows the ADC input multiplexor circuit with external components allowing 2Vrms inputs to be applied.
5K
AINOPL
10uF 10K
AINVGL AIN1L
10uF
10K
AIN2L
10uF 10K
AIN3L
10uF
10K
AIN7L
10uF 10K
AIN8L
SOURCE SELECTOR INPUTS
5K
AINOPR
10uF 10K
AINVGR AIN1R
10uF
10K
AIN2R
10uF 10K
AIN3R
10uF
10K
AIN7R
10uF 10K
AIN8R
Figure 43 ADC Input Multiplexor Confiuration
4K 10uF
MX1[1]
AUX1L/R
4K
MX1[0]
DAC1L/R BYPASSL/R
4K
MX1[2]
4K
4K
SYSTEM AUX 5.1 LINE INPUTS
10uF
MX2[1]
AUX2L/R
4K
MX2[0]
DAC2L/R
4K
4K 10uF
MX3[1]
AUX3L/R
4K
MX3[0]
4K DAC3L/R
Figure 44 Shows the 5.1Channel Input Multiplexor Configuration
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Product Preview
WM8777
EXTERNAL S/PDIF INPUT CIRCUIT CONFIGURATION
The SPIN, GPIO1, GPIO2, and GPIO3 pads can be configured to accept either CMOS or S/PDIF input signals. In S/PDIF mode an A.C. coupled input signal is applied to Vin. A hysteresis comparator buffers this signal and converts it to CMOS to drive on-chip. In CMOS mode the S/PDIF circuit is disabled and the signal is buffered using standard CMOS logic.
To allow an S/PDIF signal to be received correctly the incoming signal must be A.C. coupled. The recommended off-chip input configuration for this is shown below:
0.1F Vin 75 WM8777 Rx
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WM8777
RECOMMENDED ANALOGUE OUTPUT EXTERNAL COMPONENTS
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It may be that a lowpass filter is required to be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8777 produces much less high frequency output noise than competitors devices). This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 45 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
1.0nF 10uF 1.8k 7.5k
VOUT1L
47k 680pF 4.7k 4.7k
51
OP_FIL
VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R VOUT4L VOUT4R
OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL
Figure 45 Recommended Post DAC Filter Circuit
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Product Preview
WM8777
PACKAGE DIMENSIONS
FT: 100 PIN TQFP (14 x 14 x 1.0 mm)
D D1 100 1 e 75 74
DM036.A
b
E1
E
25 26 A1 50
51
A A2
-C0.1 C
SEATING PLANE
Symbols A A1 A2 b c D D1 E E1 e L ccc REF:
Dimensions (mm) MIN NOM MAX --------1.60 0.05 ----0.15 1.35 1.40 1.45 0.17 0.22 0.27 --------0.17 16.20 16.00 15.80 14.00 14.05 13.95 15.80 16.00 16.20 13.95 14.00 11.05 0.50 BSC 0.50 0.60 0.75 o o o 3.5 7 0 Tolerances of Form and Position 0.08 JEDEC.95, MS-026
c
L
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABA. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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WM8777 IMPORTANT NOTICE
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Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknoPAIFRX_WLedgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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